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| this is information on a product in full production. april 2013 doc id 17943 rev 5 1/129 1 stm8l151x8 stm8l152x8 stm8l151r6 stm8l152r6 8-bit ultralow power mcu, up to 64 kb flash + 2 kb data eeprom, rtc, lcd, timers, usarts, i2c, spis, adc, dac, comparators datasheet ? production data features operating conditions ? operating power supply: 1.65 to 3.6 v (without bor), 1.8 to 3.6 v (with bor) ? temp. range: -40 to 85, 105 or 125 c low power features ? 5 low power modes: wait, low power run (5.9 a), low power wait (3 a), active-halt with full rtc (1.4 a), halt (400 na) ? consumption: 200 a/mhz+330 a ? fast wake up from halt mode (4.7 s) ? ultra low leakage per i/0: 50 na advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq: 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources reset and supply management ? low power, ultrasafe bor reset with 5 programmable thresholds ? ultralow power por/pdr ? programmable voltage detector (pvd) clock management ? 32 khz and 1-16 mhz crystal oscillators ? internal 16 mhz factory-trimmed rc and 38 khz low consumption rc ? clock security system low power rtc ? bcd calendar with alarm interrupt, ? digital calibration with +/- 0.5ppm accuracy ? advanced anti-tamper detection dma ? 4 ch. for adc, dacs, spis, i 2 c, usarts, timers, 1 ch. for memory-to-memory lcd: 8x40 or 4x44 w/ step-up converter 12-bit adc up to 1 msps/28 channels ? temp. sensor and internal ref. voltage memories ? up to 64 kb of flash memory with up to 2 kb of data eeprom with ecc and rww ? flexible write/read protection modes ? up to 4 kb of ram 2x12-bit dac (dual mo de) with output buffer 2 ultralow power comparators ? 1 with fixed threshold and 1 rail to rail ? wakeup capability timers ? three 16-bit timers with 2 channels (ic, oc, pwm), quadrature encoder ? one 16-bit advanced control timer with 3 channels, supporting motor control ? one 8-bit timer with 7-bit prescaler ? 1 window and 1 independent watchdog ? beeper timer with 1, 2 or 4 khz frequencies communication interfaces ? two synchronous serial interface (spi) ?fast i 2 c 400 khz smbus and pmbus ? three usarts (iso 7816 interface + irda) up to 67 i/os, all mappab le on interrupt vectors up to 16 capacitive sensing channels supporting touchkey, proximity, linear touch and rotary touch sensors fast on-chip programming and non-intrusive debugging with swim, bootloader using usart 96-bit unique id table 1. device summary reference part number stm8l151x8 stm8l152x8 stm8l151c8, stm8l152c8, stm8l151r8, stm8l152r8, stm8l151m8, stm8l152m8 stm8l151r6 stm8l152r6 stm8l151r6, stm8l152r6 lqfp80 lqfp64 lqfp48 ufqfpn48 www.st.com
contents stm8l15xx8, stm8l15xr6 2/129 doc id 17943 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 stm8l ultralow power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 21 3.13 touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 16-bit advanced control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.2 16-bit general purpose timers (tim2, tim3, tim5) . . . . . . . . . . . . . . . . 22 3.14.3 8-bit basic timer (tim4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 stm8l15xx8, stm8l15xr6 contents doc id 17943 rev 5 3/129 3.15.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.2 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.2 embedded reset and power control block characteristics . . . . . . . . . . . 69 9.3.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.3.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.3.6 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3.7 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 contents stm8l15xx8, stm8l15xr6 4/129 doc id 17943 rev 5 9.3.8 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3.9 lcd controller (stm8l152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.10 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.11 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.12 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.13 12-bit dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.14 12-bit adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3.15 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 stm8l15xx8, stm8l15xr6 list of tables doc id 17943 rev 5 5/129 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. high density and medium+ density stm8l15xx low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5. high density and medium+ density stm8l15x pin description . . . . . . . . . . . . . . . . . . . . . 28 table 6. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7. factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 8. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 11. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 12. option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 13. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 14. unique id registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 19. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 20. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 21. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 22. total current consumption and timing in low power run mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 23. total current consumption in low power wait mode at vdd = 1.65 v to 3.6 v . . . . . . . . . 80 table 24. total current consumption and timing in active-halt mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 25. typical current consumption in active-halt mode, rtc clocked by lse external crystal . . 84 table 26. total current consumption and timing in halt mode at vdd = 1.65 to 3.6 v . . . . . . . . . . . 85 table 27. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 28. current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 29. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 30. lse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 31. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 32. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 33. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 34. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 35. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 36. flash program and da ta eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 37. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 38. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 39. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 40. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 41. output driving current (pa0 wi th high sink led driver capability). . . . . . . . . . . . . . . . . . . . 98 table 42. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 43. spi1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 44. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 45. lcd characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 list of tables stm8l15xx8, stm8l15xr6 6/129 doc id 17943 rev 5 table 46. reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 47. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 48. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 49. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 50. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 51. dac accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 52. dac output on pb4-pb5-pb6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 table 53. adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 54. adc1 accuracy with vdda = 3.3 v to 2.5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 55. adc1 accuracy with vdda = 2.4 v to 3.6 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 56. adc1 accuracy with vdda = vref+ = 1.8 v to 2.4 v. . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 57. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 58. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 59. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 60. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 table 61. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 62. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 63. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 64. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 123 table 65. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 124 table 66. ufqfpn48 ? ultra thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 67. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 68. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 stm8l15xx8, stm8l15xr6 list of figures doc id 17943 rev 5 7/129 list of figures figure 1. high density and medium+ density stm8l15xx device block diagram . . . . . . . . . . . . . . 13 figure 2. clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. stm8l151m8 80-pin package pinout (without lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4. stm8l152m8 80-pin package pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5. stm8l151r8 and stm8l151r6 64-pin pinout (without lcd). . . . . . . . . . . . . . . . . . . . . . 26 figure 6. stm8l152r8 and stm8l152r6 64-pin pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. stm8l151c8 48-pin pinout (without lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. stm8l152c8 48-pin pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 12. power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 13. typical i dd(run) from ram vs. v dd (hsi clock source), f cpu =16 mhz . . . . . . . . . . . . . . 74 figure 14. typical i dd(run) from flash vs. v dd (hsi clock source), f cpu = 16 mhz . . . . . . . . . . . . . 74 figure 15. typical i dd(wait) from ram vs. v dd (hsi clock source), f cpu = 16 mhz . . . . . . . . . . . . . . 77 figure 16. typical i dd(wait) from flash (hsi clock source), f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . 77 figure 17. typical i dd(lpr) vs. v dd (lsi clock source), all peripherals off . . . . . . . . . . . . . . . . . . . . 79 figure 18. typical i dd(lpw) vs. v dd (lsi clock source), all peripherals off . . . . . . . . . . . . . . . . . . . 81 figure 19. typical idd(ah) vs. v dd (lsi clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 20. typical idd(halt) vs. v dd (internal reference voltage off) . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 21. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 22. lse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 23. typical hsi frequency vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 24. typical lsi clock source frequency vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 25. typical vil and vih vs. vdd (standard i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 26. typical vil and vih vs. vdd (true open drain i/os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 27. typical pull-up resistance r pu vs. v dd with vin=vss. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 28. typical pull-up current i pu vs. v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 29. typical vol @ vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 30. typical vol @ vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 31. typical vol @ vdd = 3.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 32. typical vol @ vdd = 1.8 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 33. typical vdd - voh @ vdd = 3.0 v (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 34. typical vdd - voh @ vdd = 1.8 v (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 35. typical nrst pull-up resistance r pu vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 36. typical nrst pull-up current i pu vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 37. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 38. spi1 timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 39. spi1 timing diagram - slave mode and cpha=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 40. spi1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 figure 41. typical application with i2c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 42. adc1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 43. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 44. maximum dynamic current consumption on v ref+ supply pin during adc conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 45. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 117 figure 46. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . 117 figure 47. 80-pin low profile quad flat package (14 x 14 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 list of figures stm8l15xx8, stm8l15xr6 8/129 doc id 17943 rev 5 figure 48. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 123 figure 49. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 50. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 51. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 52. ufqfpn48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 53. recommended footprint (dimensions in mm) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 stm8l15xx8, stm8l15xr6 introduction doc id 17943 rev 5 9/129 1 introduction this document describes the features, pinout, mechanical data and ordering information for: high density stm8l15xxx devices: stm8l151x8 and stm8l152x8 microcontrollers with a flash memory density of 64 kbytes. medium+ density stm8l15xxx devices : stm8l151r6 and stm8l152r6 microcontrollers with flash memory density of 32 kbytes. for further details on the stmicroelectroni cs ultralow power family please refer to section 2.3: ultralow power continuum on page 12 . for detailed information on device operation and registers, refer to the reference manual (rm0031). for information on to the flash program memory and data eeprom, refer to the programming manual (pm0054). for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). 2 description the high density and medium+ density stm8l15xx ultralow power devices feature an enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application debugging and ultrafast flash programming. all high density and medium+ density stm8l15xx microcontrollers feature embedded data eeprom and low power low-voltage si ngle-supply program flash memory. the devices incorporate an extensive range of enhanced i/os and peripherals, a 12-bit adc, two dacs, two comparators, a real-time clock, four 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as two spis, an i 2 c interface, and three usarts. a 8x40 or 4x44-segment lcd is available on the stm8l152x8 devices. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families including 32-bit families. this ma kes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. description stm8l15xx8, stm8l15xr6 10/129 doc id 17943 rev 5 2.1 stm8l ultralow power 8-bit family benefits high density and medium+ density stm8l15xx devices are part of the stm8l ultralow power family providing the following benefits: integrated system ? up to 64 kbytes of high-density embedded flash program memory ? up to 2 kbytes of data eeprom ? up to 4 kbytes of ram ? internal high-speed and low-power low speed rc. ? embedded reset ultralow power consumption ? 1 a in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for lo w power wait mode and low power run mode advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory-to-memory or peripheral-to-memory access. short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals. ? wide choice of development tools stm8l ultralow power microcontrollers can operate either from 1.8 to 3.6 v (down to 1.65 v at power-down) or from 1.65 to 3.6 v. they are available in the -40 to +85 c and -40 to +125 c temperature ranges. these features make the stm8l ultralow powe r microcontroller families suitable for a wide range of applications: medical and handheld equipment application control and user interface pc peripherals, gaming, gps and sport equipment alarm systems, wired and wireless sensors metering the devices are offered in four different packages from 48 to 80 pins. different sets of peripherals are included depending on the device. refer to section 3 for an overview of the complete range of peripherals proposed in this family. all stm8l ultralow power products are based on the same architecture with the same memory mapping and a coherent pinout. figure 1 shows the block diagram of the high density and medium+ density stm8l15xx families. stm8l15xx8, stm8l15xr6 description doc id 17943 rev 5 11/129 2.2 device overview table 2. high density and medium+ density stm8l15xx low power device features and peripheral counts features stm8l15xc8 stm8l1 5xr8 stm8l15xm8 stm8l15xr6 flash (kbytes) 64 64 64 32 data eeprom (kbytes) 2 1 ram (kbytes) 4 4 4 2 lcd 8x24 or 4x28 (1) 8x36 or 4x40 (1) 8x40 or 4x44 (1) 8x36 or 4x40 (1) timers basic 1 (8-bit) 1 (8-bit) 1 (8-bit) 1 (8-bit) general purpose 3 (16-bit) 3 (16-bit) 3 (16-bit) 3 (16-bit) advanced control 1 (16-bit) 1 (16-bit) 1 (16-bit) 1 (16-bit) communication interfaces spi 2 2 2 2 i2c 1 1 1 1 usart 3 3 3 3 gpios 41 (2) 54 (2) 68 (2) 54 (2) 12-bit synchronized adc (number of channels) 1 (25) 1 (28) 1 (28) 1 (28) 12-bit dac number of channels 2 2 2 2 2 2 2 2 comparators (comp1/comp2) 2 2 2 2 others rtc, window watchdog, independent watchdog, 16-mhz and 38-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 to 3.6 v (down to 1.65 v at power-down) with bor 1.65 to 3.6 v without bor operating temperature ? 40 to +85 c / ? 40 to +105 c / ? 40 to +125 c packages ufqfpn48 lqfp48 lqfp64 lqfp80 lqfp64 1. stm8l152xx versions only. 2. the number of gpios given in this table includes the nrs t/pa1 pin but the application can use the nrst/pa1 pin as general purpose output only (pa1). description stm8l15xx8, stm8l15xr6 12/129 doc id 17943 rev 5 2.3 ultralow power continuum the ultralow power stm8l151xx and stm8l152xx are fully pin-to-pin, software and feature compatible. besides the full compatibility within the fam ily, the devices are part of stmicroelectronics microcontrollers ultralow power strategy which also includes stm8l101xx and stm32 l15xxx. the stm8l and stm32l families allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultralow leakage process. note: 1 the stm8l151xx and stm8l152xx are pin-to-pin compatible with stm8l101xx devices. 2 the stm32l family is pin-to-pin compatible with the general purpose stm32f family. please refer to stm32l15xx documentation for more information on these devices. performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultralow power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l151xx/152xx and stm32l15xx share identical peripherals which ensure a very easy migration from one family to another: analog peripherals: adc1, dac1/dac2, and comparators comp1/comp2 digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and optimize performance, the stm8l15xx and st m32l15xx devices use a common architecture: same power supply range from 1.65 to 3.6 v. for stm8l101xx and medium density stm8l15xx, the power supply must be above 1.8 v at power-on, and go below 1.65 v at power-down. architecture optimized to reach ultralow consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultrasafe reset: same reset strategy for both stm8l15xx and stm32l15xx including power-on reset, power-down reset, brownout reset and programmable voltage detector. features st utralow power continuum also lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 13/129 3 functional overview figure 1. high density and medium+ density stm8l15xx device block diagram 1. legend : af: alternate function adc: analog-to-digital converter bor: brownout reset dma: direct memory access dac: digital-to-analog converter i2c: inter-integrated circuit multimaster interface iwdg: independent watchdog a i b # l o c k c o n t r o l l e r a n d # 3 3 # l o c k s ! d d r e s s c o n t r o l a n d d a t a b u s e s + b y t e + b y t e 2 ! - t o c o r e a n d p e r i p h e r a l s ) 7 $ ' k ( z c l o c k 0 o r t ! 0 o r t " 0 o r t # 0 o w e r 6 / , 4 2 % ' , # $ d r i v e r 7 7 $ ' u p t o + b y t e 0 o r t $ 0 o r t % " e e p e r 2 4 # m e m o r y 0 r o g r a m $ a t a % % 0 2 / - 6 $ $ 6 $ $ 6 $ $ 6 6 3 3 3 7 ) - 3 # , 3 $ ! 3 0 ) ? - / 3 ) 3 0 ) ? - ) 3 / 3 0 ) ? 3 # + 3 0 ) ? . 3 3 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + ! $ # ? ) . x # / - 0 ? ) . 0 # / - 0 # / - 0 # / - 0 ? ) . 0 6 $ $ ! 6 3 3 ! 3 - " 6 $ $ ! 6 3 3 ! 4 e m p s e n s o r b i t ! $ # 6 2 % & 6 b i t $ ! # b i t $ ! # . 2 3 4 0 ! ; = 0 " ; = 0 # ; = 0 $ ; = 0 % ; = 0 & ; = " % % 0 ! , ! 2 - # ! , ) " 4 ! - 0 3 % ' x # / - x 0 / 2 0 $ 2 / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 t o " / 2 0 6 $ 0 6 $ ? ) . 2 % 3 % 4 $ - ! c h a n n e l s c h a n n e l s c h a n n e l s c h a n n e l s # / - 0 ? ) . - 6 , # $ t o 6 , # $ b o o s t e r ) n t e r n a l r e f e r e n c e v o l t a g e 6 2 % & ) . 4 o u t ) 2 ? 4 ) - - ( z o s c i l l a t o r - ( z i n t e r n a l 2 # k ( z o s c i l l a t o r 3 4 - # o r e b i t 4 i m e r b i t 4 i m e r k ( z i n t e r n a l 2 # ) n t e r r u p t c o n t r o l l e r b i t 4 i m e r $ e b u g m o d u l e 3 7 ) - b i t 4 i m e r ) n f r a r e d i n t e r f a c e 3 0 ) ) # 5 3 ! 2 4 6 2 % & 0 o r t & b i t 4 i m e r c h a n n e l s 3 0 ) 3 0 ) ? - / 3 ) 3 0 ) ? - ) 3 / 3 0 ) ? 3 # + 3 0 ) ? . 3 3 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + 5 3 ! 2 4 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + 5 3 ! 2 4 0 ' ; = 0 o r t ' 0 ( ; = 0 o r t ( 0 ) ; = 0 o r t ) y p s y $ ! # ? / 5 4 b i t $ ! # b i t $ ! # $ ! # ? / 5 4 * ' u p t o u p t o functional overview stm8l15xx8, stm8l15xr6 14/129 doc id 17943 rev 5 lcd: liquid crystal display por/pdr: power on reset / power-down reset rtc: real-time clock spi: serial peripheral interface swim: single wire interface module usart: universal synchronous asyn chronous receiver transmitter wwdg: window watchdog 3.1 low power modes the high density and medium+ density stm8l15xx devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: wait mode : cpu clock is stopped, but selected peripherals keep running. an internal or external interrupt or a reset can be used to exit the microcontroller from wait mode (wfe or wfi mode). low power run mode : the cpu and the selected peripherals are running. execution is done from ram with a low speed oscilla tor (lsi or lse). fl ash memory and data eeprom are stopped and the voltage regulator is configured in ultralow power mode. the microcontroller enters low power run mode by software and can exit from this mode by software or by a reset. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power wait mode: this mode is entered when executing a wait for event in low power run mode. it is similar to low power run mode except that the cpu clock is stopped. the wakeup from this mode is triggered by a reset or by an internal or external event (peripheral event generated by the timers, serial interfaces, dma controller (dma1), comparators and i/o ports). when the wakeup is triggered by an event, the system goes back to low power run mode. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. active-halt mode : cpu and peripheral clocks are stopped, except rtc. the wakeup can be triggered by rtc interrupts, external interrupts or reset. halt mode : cpu and peripheral clocks are stopped, the device remains powered on. the ram content is preserved. the wakeup is triggered by an external interrupt or reset. a few peripherals have also a wake up from halt capability. switching off the internal reference voltage reduces power consumption. through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 s. stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 15/129 3.2 central processing unit stm8 3.2.1 advanced stm8 core the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing, and 80 instructions. architecture and registers harvard architecture 3-stage pipeline 32-bit wide program memory bus - si ngle cycle fetching most instructions x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16 mbyte linear memory space 16-bit stack pointer - access to a 64 kbyte level stack 8-bit condition code register - 7 condition flags for the result of the last instruction addressing 20 addressing modes indexed indirect addressing mode for lookup tables located anywhere in the address space stack pointer relative addressing mode for local variables and parameter passing instruction set 80 instructions with 2-byte average instruction size standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division bit manipulation data transfer between stack and accumulator (push/pop) with direct stack access data transfer using the x and y registers or direct memory-to-memory transfers 3.2.2 interrupt controller the high density and medium+ density stm8l15xxdevices feature a nested vectored interrupt controller: nested interrupts with 3 software priority levels 32 interrupt vectors with hardware priority up to 40 external interrupt sources on 11 vectors trap and reset interrupts functional overview stm8l15xx8, stm8l15xr6 16/129 doc id 17943 rev 5 3.3 reset and supply management 3.3.1 power supply scheme the device requires a 1.65 v to 3.6 v operating supply voltage (v dd ). the external power supply pins must be connected as follows: v ss1 , v dd1 , v ss2 , v dd2 , v ss3 , v dd3 , v ss4 , v dd4 = 1.65 to 3.6 v: external power supply for i/os and for the internal regulator. provided externally through v dd pins, the corresponding ground pin is v ss . v ss1 /v ss2 /v ss3 /v ss4 and v dd1 /v dd2 /v dd3 /v dd4 must not be left unconnected. v ssa , v dda = 1.65 to 3.6 v: external power supplies for analog peripherals (minimum voltage to be applied to v dda is 1.8 v when the adc1 is used). v dda and v ssa must be connected to v dd and v ss , respectively. v ref+ , v ref- (for adc1): external reference voltage for adc1. must be provided externally through v ref+ and v ref- pin. v ref+ (for dac1/2): external voltage reference for dac1 and dac2 must be provided externally through v ref+ . 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr). for the device sales types without the ?d? option (see section 11: ordering information scheme ), it is coupled with a brownout reset (bor) circuitry. it that case the device operates between 1.8 and 3.6 v, bor is always active and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently (in which case, the v dd min. value at power-down is 1.65 v). five bor thresholds are available through option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the bor) in halt mode. the device remains in reset state when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. note: for device sales types with the ?d? option (see section 11: ordering information scheme ) bor is permanently disabled and the device operates between 1.65 and 3.6 v. in this case it is not possible to enable bor through the option bytes. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 17/129 3.3.3 voltage regulator the high density and medium+ density stm8l15xx devices embed an internal voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: main voltage regulator mode (mv r) for run, wait for interrupt (wfi) and wait for event (wfe) modes. low power voltage regulator mode (lpvr) for halt, active-halt, low power run and low power wait modes. when entering halt or active-halt modes, the system automatically switches from the mvr to the lpvr in order to reduce current consumption. 3.4 clock management the clock controller distributes the system clock (sysclk) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. system clock sources: 4 different clock sources can be used to drive the system clock: ? 1-16 mhz high speed external crystal (hse) ? 16 mhz high speed internal rc oscillator (hsi) ? 32.768 low speed external crystal (lse) ? 38 khz low speed internal rc (lsi) rtc and lcd clock sources: the above four sources can be chosen to clock the rtc and the lcd, whatever the system clock. startup clock: after reset, the microcontroller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the system clock is automatically switched to hsi. configurable main clock output (cco): this outputs an external clock for use by the application. functional overview stm8l15xx8, stm8l15xr6 18/129 doc id 17943 rev 5 figure 2. clock tree diagram 3.5 low power real-time clock the real-time clock (rtc) is an independent binary coded decimal (bcd) timer/counter. six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day months are made automatically. the subsecond field can also be read in binary format. the calendar can be corrected from 1 to 32767 rtc clock pulses. this allows to make a synchronization to a master clock. the rtc offers a digital calibration which allows an accuracy of +/-0.5 ppm. it provides a programmable alarm and programmable periodic interrupts with wakeup from halt capability. periodic wakeup time using the 32.768 khz lse with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. with a different resolution, the wakeup time can reach 36 hours periodic alarms based on the calendar can also be generated from lse period to every year a clock security system detects a failure on lse, and can provide an interrupt with wakeup capability. the rtc clock can automatically switch to lsi in case of lse failure. the rtc also provides 3 anti-tamper detection pins. this detection embeds a programmable filter and can wakeup the mcu. ( 3 % / 3 # - ( z ( 3 ) 2 # - ( z , 3 ) 2 # k ( z , 3 % / 3 # k ( z ( 3 ) , 3 ) 2 4 # p r e s c a l e r 0 # , + t o p e r i p h e r a l s 2 4 # # , + t o , # $ t o ) 7 $ ' 3 9 3 # , + ( 3 % , 3 ) , 3 % / 3 # ? / 5 4 / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? ) . c l o c k o u t p u t # # / p r e s c a l e r ( 3 ) , 3 ) ( 3 % , 3 % # # / t o c o r e a n d m e m o r y 3 9 3 # , + 0 r e s c a l e r ) 7 $ ' # , + 2 4 # 3 % , ; = , 3 % # , + " % % 0 3 % , ; = t o " % % 0 " % % 0 # , + a i # 3 3 c o n f i g u r a b l e 0 e r i p h e r a l # l o c k e n a b l e b i t s t o 2 4 # 2 4 # # , + c l o c k e n a b l e b i t , # $ # , + t o , # $ 3 9 3 # , + ( a l t c l o c k e n a b l e b i t , # $ p e r i p h e r a l 2 4 # # , + , # $ p e r i p h e r a l # 3 3 ? , 3 % stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 19/129 3.6 lcd (liquid crystal display) the lcd is only availabl e on stm8l152xx devices. the liquid crystal display drives up to 8 common terminals and up to 40 segment terminals to drive up to 320 pixels. it can also be configured to drive up to 4 common and 44 segments (up to 176 pixels). internal step-up converter to guarantee contrast control whatever v dd . static 1/2, 1/3, 1/4, 1/8 duty supported. static 1/2, 1/3, 1/4 bias supported. phase inversion to reduce power consumption and emi. up to 8 pixels which can programmed to blink. the lcd controller can operate in halt mode. note: unnecessary segments and common pins can be used as general i/o pins. 3.7 memories the high density and medium+ density stm8l15xx devices have the following main features: up to 4 kbytes of ram the non-volatile memory is divided into three arrays: ? up to 64 kbytes of medium-density embedded flash program memory ? up to 2 kbytes of data eeprom ?option bytes. the eeprom embeds the error correction code (e cc) feature. it supp orts the read-while- write (rww): it is possible to execute the code from the program matrix while programming/erasing the data matrix. the option byte protects part of the flash program memory from write and readout piracy. 3.8 dma a 4-channel direct memory access controlle r (dma1) offers a memory-to-memory and peripherals-from/to-memory tr ansfer capability. the 4 chann els are shared between the following ips with dma capability: adc1, da c1,dac2, i2c1, spi1, spi2, usart1, usart2, usart3, and the 5 timers. functional overview stm8l15xx8, stm8l15xr6 20/129 doc id 17943 rev 5 3.9 analog-to-digital converter 12-bit analog-to-digital converter (adc1) with 28 channels (including 4 fast channel), temperature sensor and internal reference voltage conversion time down to 1 s with f sysclk = 16 mhz programmable resolution programmable sampling time single and continuous mode of conversion scan capability: automatic conversion perfor med on a selected gr oup of anal og inputs analog watchdog: interrupt generation when the converted voltage is outside the programmed threshold triggered by timer note: adc1 can be served by dma1. 3.10 digital-to-analog converter 12-bit dac with 2 buffered outputs (two digital signals can be converted into two analog voltage signal outputs) synchronized update capability using timers dma capability for each channel external triggers for conversion noise-wave generation triangular-wave generation dual dac channels with independent or simultaneous conversions input reference voltage v ref+ for better resolution note: dac can be served by dma1. 3.11 ultralow power comparators the high density and medium+ density stm8l15xx devices embed two comparators (comp1 and comp2) sharing the same current bias and voltage reference. the voltage reference can be internal or external (coming from an i/o). one comparator with fixed threshold (comp1). one comparator rail to rail with fast or slow mode (comp2). the threshold can be one of the following: ? dac output ? external i/o ? internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4) the two comparators can be used together to offer a window function. they can wake up from halt mode. stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 21/129 3.12 system configuration cont roller and routing interface the system configuration controller provides the capability to remap some alternate functions on different i/o ports. tim4 and adc1 dma channels can also be remapped. the highly flexible routing interface allows application software to control the routing of different i/os to the tim1 timer input captures. it also controls the routing of internal analog signals to adc1, comp1, comp2, dac1 and the internal reference voltage v refint . it also provides a set of registers for efficiently managing the charge transfer acquisition sequence (see section 3.13: touch sensing ). 3.13 touch sensing the high density and medium+ density stm8l15xx devices provide a simple solution for adding capacitive sensing functionality to any application. capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. in the high density and medium+ density stm8l15xx devices, the acquisition sequence is managed by software and it involves analog i/o groups and the routing interface. reliable touch sensing solution can be quickly and easily implemented using the free stm8 touch sensing firmware library. 3.14 timers the high density and medium+ density stm8l15xx devices contain one advanced control timer (tim1), three 16-bit general purpose timers (tim2,tim3 and tim5) and one 8-bit basic timer (tim4). all the timers can be served by dma1. ta bl e 3 compares the features of the advanced control, general-purpose and basic timers. table 3. timer feature comparison timer counter resolution counter type prescaler factor dma1 request generation capture/compare channels complementary outputs tim1 16-bit up/down any integer from 1 to 65536 ye s 3 + 1 3 tim2 any power of 2 from 1 to 128 2 none tim3 tim5 tim4 8-bit up any power of 2 from 1 to 32768 0 functional overview stm8l15xx8, stm8l15xr6 22/129 doc id 17943 rev 5 3.14.1 16-bit advanced control timer (tim1) this is a high-end timer designed for a wide range of control applications. with its complementary outputs, dead-ti me control and center-aligned pwm capability, the field of applications is extended to motor control, lighting and half-bridge driver. 16-bit up, down and up/down autoreload counter with 16-bit prescaler 3 independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (edge and center aligned mode) and single pulse mode output 1 additional capture/compare channel which is not connected to an external i/o synchronization module to control the timer with external signals break input to force timer outputs into a defined state 3 complementary outputs with adjustable dead time encoder mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) 3.14.2 16-bit general purpose timers (tim2, tim3, tim5) 16-bit autoreload (ar) up/down-counter 7-bit prescaler adjustable to fixed power of 2 ratios (1?128) 2 individually configurable capture/compare channels pwm mode interrupt capability on various events (cap ture, compare, overflow, break, trigger) synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.14.3 8-bit basi c timer (tim4) the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase generation with interrupt generation on timer overflow or for dac trigger generation. 3.15 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. 3.15.1 window watchdog timer the window watchdog (wwdg) is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. 3.15.2 independent watchdog timer the independent watchdog peripheral (iwdg) can be used to resolve processor malfunctions due to hardware or software failures. stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 23/129 it is clocked by the internal lsi rc clock source, and thus stays active even in case of a cpu clock failure. 3.16 beeper the beeper functi on outputs a signal on the beep pin for sound gener ation. the signal is in the range of 1, 2 or 4 khz. 3.17 communication interfaces 3.17.1 spi the serial peripheral interfaces (spi1 and spi2) provide half/ full duplex synchronous serial communication with external devices. maximum speed: 8 mbit/s (f sysclk /2) both for master and slave full duplex synchronous transfers simplex synchronous transfers on 2 lines with a possible bidirectional data line master or slave operation - selectable by hardware or software hardware crc calculation slave/master selection input pin note: spi1 and spi2 can be served by the dma1 controller. 3.17.2 i 2 c the i 2 c bus interface (i2c1) provi des multi-master capability, and controls all i2c bus- specific sequencing, protocol, arbitration and timing. master, slave and multi-master capability standard mode up to 100 khz and fast speed modes up to 400 khz. 7-bit and 10-bit addressing modes. smbus 2.0 and pmbus support hardware crc calculation note: i 2 c1 can be served by the dma1 controller. functional overview stm8l15xx8, stm8l15xr6 24/129 doc id 17943 rev 5 3.17.3 usart the usart interfaces (usart1, usart2 and usart3) allow full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. 1 mbit/s full duplex sci spi1 emulation high precision baud rate generator smartcard emulation irda sir encoder decoder single wire half duplex mode note: usart1, usart2 and usart3 can be served by the dma1 controller. 3.18 infrared (ir) interface the high density and medium+ density stm8l15xx devices contain an infrared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. 3.19 development support development tools development tools for the stm8 microcontrollers include: the stice emulation system offe ring tracing and code profiling the stvd high-level language debugger including c compiler, assembler and integrated development environment the stvp flash programming software the stm8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. single wire data interface (swim) and debug module the debug module with its single wire data interface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single wire interface is used for direct access to the debugging module and memory programming. the interface can be activated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, cpu operation can also be monitored in real- time by means of shadow registers. bootloader a bootloader is available to reprogram the flash memory using the usart1, usart2, usart3 (usarts in asynchronous mode), spi1 or spi2 interfaces. the reference document for the bootloader is um0560: stm8 bootloader user manual . stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 25/129 4 pin description figure 3. stm8l151m8 80-pin package pinout (without lcd) 1. pin 22 is reserved and must be tied to v dd . figure 4. stm8l152m8 80-pin package pinout (with lcd) a i . 2 3 4 0 ! 0 ( 0 ( 0 ( 0 ! 0 ! 2 e s 0 % 0 % 0 $ 0 $ 0 $ 0 ( 0 % 0 $ 0 % 0 % 0 ! 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 6 $ $ 6 3 3 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ( 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 ' 0 ' 0 ' 0 ( 0 ( 0 ( 0 " 0 " 6 $ $ 6 3 3 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 ' 0 ' 0 ' 0 ' 6 3 3 6 $ $ 0 ) 0 ) 0 ) 0 ) 0 ' a i . 2 3 4 0 ! 0 ( 0 ( 0 ( 0 ! 0 ! 6 , # $ 0 % 0 % 0 $ 0 $ 0 $ 0 ( 0 % 0 $ 0 % 0 % 0 ! 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 6 $ $ 6 3 3 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ( 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 ' 0 ' 0 ' 0 ( 0 ( 0 ( 0 " 0 " 6 $ $ 6 3 3 0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 ' 0 ' 0 ' 0 ' 6 3 3 6 $ $ 0 ) 0 ) 0 ) 0 ) 0 ' pin description stm8l15xx8, stm8l15xr6 26/129 doc id 17943 rev 5 figure 5. stm8l151r8 and stm8l151r6 64-pin pinout (without lcd) 1. pin 18 is reserved and must be tied to v dd . figure 6. stm8l152r8 and stm8l152r6 64-pin pinout (with lcd) . 2 3 4 0 ! 0 ! 0 ! 0 ! 2 e s 0 % 0 % 0 $ 0 $ 0 $ 0 % 0 $ 0 % 0 % 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 6 $ $ 6 3 3 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 ' 0 ' 0 ' 0 ' 0 " 0 " 0 & 0 & 0 & 0 & 0 & 0 ' 0 ' 0 ' 0 ' 6 3 3 6 $ $ a i . 2 3 4 0 ! 0 ! 0 ! 0 ! 6 , # $ 0 % 0 % 0 $ 0 $ 0 $ 0 % 0 $ 0 % 0 % 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 6 $ $ 6 3 3 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 ' 0 ' 0 ' 0 ' 0 " 0 " 0 & 0 & 0 & 0 & 0 & 0 ' 0 ' 0 ' 0 ' 6 3 3 6 $ $ a i stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 27/129 figure 7. stm8l151c8 48-pin pinout (without lcd) 1. pin 13 is reserved and must be tied to v dd . figure 8. stm8l152c8 48-pin pinout (with lcd) . 2 3 4 0 ! 0 ! 0 ! 0 ! 0 % 0 % 0 $ 0 $ 0 $ 0 % 0 $ 0 % 0 % 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 " 6 3 3 6 $ $ 0 " 2 e s a i . 2 3 4 0 ! 0 ! 0 ! 0 ! 6 , # $ 0 % 0 % 0 $ 0 $ 0 $ 0 % 0 $ 0 % 0 % 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 " 6 3 3 6 $ $ 0 " a i pin description stm8l15xx8, stm8l15xr6 28/129 doc id 17943 rev 5 table 4. legend/abbreviation type i= input, o = output, s = power supply level ft: five-volt tolerant output hs = high sink/source (20 ma) port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state a fter reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). table 5. high density and medium+ density stm8l15x pin description pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp 1 - - ph0/lcd seg 36 (3) i/o ft (5) x xxhsxx port h0 lcd segment 36 2 - - ph1/lcd seg 37 (3) i/o ft (5) x xxhsxx port h1 lcd segment 37 3 - - ph2/lcd seg 38 (3) i/o ft (5) x xxhsxx port h2 lcd segment 38 4 - - ph3/lcd seg 39 (3) i/o ft (5) x xxhsxx port h3 lcd segment 39 6 2 2 nrst/pa1 (1) i/o x hs x reset pa 1 733 pa2/osc_in/ [usart1_tx] (2) / [spi1_miso] (2) i/o x xxhsxx port a2 hse oscillator input / [usart1 transmit] / [spi1 master in- slave out] / 844 pa3/osc_out/ [usart1_rx] (2) /[ spi1_mosi] (2) i/o x xxhsxx port a3 hse oscillator output / [usart1 receive]/ [spi1 master out/slave in] / 955 pa4/tim2_bkin/ [tim2_etr] (2) lcd_com0 (3) /adc1_in2 [comp1_inp] i/o ft (5) x xxhsxx port a4 timer 2 - break input / / [timer 2 - trigger] / lcd com 0 / adc1 input 2/ [comparator 1 positive input] 10 6 6 pa5/tim3_bkin/ [tim3_etr] (2) / lcd_com1 (3) /adc1_in1/ [comp1_inp] i/o ft (5) x xxhsxx port a5 timer 3 - break input / [timer 3 - trigger] / lcd_com 1 / adc1 input 1/ [comparator 1 positive input] 11 7 7 pa6/adc1_trig/ lcd_com2 (3) /adc1_in0/ [comp1_inp] i/o ft (5) x xxhsxx port a6 adc1 - trigger / lcd_com2 / adc1 input 0/ [comparator 1 positive input] stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 29/129 12 8 8 pa7/lcd_seg0 (3) / tim5_ch1 i/o ft (5) x xxhsxx port a7 lcd segment 0 / tim5 channel 1 39 31 24 pb0 (4) /tim2_ch1/ lcd_seg10 (3) /adc1_in18 / [comp1_inp] i/o ft (5) x xxhsxx port b0 timer 2 - channel 1 /lcd segment 10/ adc1_in18/ [comparator 1 positive input] 40 32 25 pb1/tim3_ch1/ lcd_seg11 (3) /adc1_in17 / [comp1_inp] i/o ft (5) x xxhsxx port b1 timer 3 - channel 1 / lcd segment 11 / adc1_in17/ [comparator 1 positive input] 41 33 26 pb2/ tim2_ch2/lcd_seg12 (3) / adc1_in16/ [comp1_inp] i/o ft (5) x xxhsxx port b2 timer 2 - channel 2 / lcd segment 12 / adc1_in16/ [comparator 1 positive input] 42 34 27 pb3/tim2_etr/ lcd_seg13 (3) /adc1_in15 / [comp1_inp] i/o ft (5) x xxhsxx port b3 timer 2 - trigger / lcd segment 13 /adc1_in15/ [comparator 1 positive input] 43 35 - pb4 (4) /spi1_nss/ lcd_seg14 (3) /adc1_in14 / [comp1_inp] i/o ft (5) x xxhsxx port b4 spi1 master/slave select / lcd segment 14 / adc1_in14/ [comparator 1 positive input] --28 pb4 (4) /spi1_nss/ lcd_seg14 (3) /adc1_in14 /dac_out2/ [comp1_inp] i/o ft (5) x xxhsxx port b4 spi1 master/slave select / lcd segment 14 / adc1_in14 / dac channel 2 output/ [comparator 1 positive input] 44 36 - pb5/spi1_sck/ lcd_seg15 (3) /adc1_in13 / [comp1_inp] i/o ft (5) x xxhsxx port b5 spi1 clock / lcd segment 15 / adc1_in13/ [comparator 1 positive input] --29 pb5/spi1_sck/ lcd_seg15 (3) /adc1_in13 /dac_out2/ [comp1_inp] i/o ft (5) x xxhsxx port b5 [spi1 clock] / lcd segment 15 / adc1_in13 / dac channel 2 output/ [comparator 1 positive input] 45 37 - pb6/spi1_mosi/ lcd_seg16 (3) /adc1_in12 / [comp1_inp] i/o ft (5) x xxhsxx port b6 spi1 master out/slave in/ lcd segment 16 / adc1_in12/ [comparator 1 positive input] table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp pin description stm8l15xx8, stm8l15xr6 30/129 doc id 17943 rev 5 --30 pb6/spi1_mosi/ lcd_seg16 (3) /adc1_in12 /dac_out2/ [comp1_inp] i/o ft (5) x xxhsxx port b6 spi1 master out/ slave in / lcd segment 16 / adc1_in12 / dac channel 2 output/ [comparator 1 positive input] 46 38 31 pb7/spi1_miso/ lcd_seg17 (3) / adc1_in11/ [comp1_inp] i/o ft (5) x xxhsxx port b7 spi1 master in- slave out/ lcd segment 17 / adc1_in11/ [comparator 1 positive input] 65 53 37 pc0/i2c1_sda i/o ft (5) x xt (6) port c0 i2c1 data 66 54 38 pc1/i2c1_scl i/o ft (5) x xt (6) port c1 i2c1 clock 69 57 41 pc2/usart1_rx/ lcd_seg22/adc1_in6/ [comp1_inp] /vrefint i/o ft (5) x xxhsxx port c2 usart1 receive / lcd segment 22 / adc1_in6/ [comparator 1 positive input] /internal reference voltage output --42 pc3/usart1_tx/ lcd_seg23 (3) / adc1_in5 i/o ft (5) x xxhsxx port c3 usart1 transmit / lcd segment 23 / adc1_in5 70 58 - pc3/usart1_tx/ lcd_seg23 (3) / adc1_in5/ [comp2_inm] / [comp1_inp] i/o ft (5) x xxhsxx port c3 usart1 transmit / lcd segment 23 / adc1_in5 / [comparator 2 negative input] / [comparator 1 input positive] 71 59 - pc4/usart1_ck/ i2c1_smb/ [cco] (2) / lcd_seg24 (3) / adc1_in4/ [comp2_inm] / [comp1_inp] i/o ft (5) x xxhsxx port c4 usart1 synchronous clock / i2c1_smb / [configurable clock output] / lcd segment 24 / adc1_in4 / [comparator 2 negative input] / [comparator 1 positive input] table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 31/129 --43 pc4/usart1_ck/ i2c1_smb/ [cco] (2) / lcd_seg24 (3) /adc1_in4/ [comp2_inm] / [comp1_inp] / [lcd_com4] i/o ft (5) x xxhsxx port c4 usart1 synchronous clock / i2c1_smb / [configurable clock output] / lcd segment 24 / adc1_in4 / [comparator 2 negative input] / [comparator 1 positive input] / [lcd_com4] (3) 72 60 44 pc5/osc32_in / [spi1_nss] (2) / [usart1_tx] (2) i/o ft (5) x xxhsxx port c5 lse oscillator input / [spi1 master/slave select] / [usart1 transmit] 73 61 45 pc6/osc32_out/ [spi1_sck] (2) / [usart1_rx] (2) i/o ft (5) x xxhsxx port c6 lse oscillator output / [spi1 clock] / [usart1 receive] 74 62 - pc7/lcd_seg25 (3) / adc1_in3/ [comp2_inm] / [comp1_inp] i/o ft (5) x xxhsxx port c7 lcd segment 25 /adc1_in3/ [comparator 2 negative input] / [comparator 1 positive input] --46 pc7/lcd_seg25 (3) / adc1_in3/usart3_ck/ [comp2_inm] / [comp1_inp] / [lcd_com5] i/o ft (5) x xxhsxx port c7 lcd segment 25 /adc1_in3/ usart3 synchronous clock/ [comparator 2 negative input] / [comparator 1 positive input] / [lcd_com5] (3) 29 25 20 pd0/tim3_ch2/ [adc1_trig] (2) / lcd_seg7 (3) /adc1_in22/ [comp2_inp] i/o ft (5) x xxhsxx port d0 timer 3 - channel 2 / [adc1_trigger] / lcd segment 7 / adc1_in22 / [comparator 2 positive input] 30 26 21 pd1/tim3_etr/ lcd_com3 (3) /adc1_in21/ [comp1_inp] // [comp2_inp] i/o ft (5) x xxhsxx port d1 timer 3 - trigger / lcd_com3 / adc1_in21 / [comparator 1 positive input] / [comparator 2 positive input] 31 27 22 pd2/tim1_ch1 /lcd_seg8 (3) /adc1_in20/ [comp1_inp] i/o ft (5) x xxhsxx port d2 timer 1 - channel 1 / lcd segment 8 / adc1_in20/ [comparator 1 positive input] table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp pin description stm8l15xx8, stm8l15xr6 32/129 doc id 17943 rev 5 32 28 23 pd3/ tim1_etr/ lcd_seg9 (3) / adc1_in19/ [comp1_inp] i/o ft (5) x xxhsxx port d3 timer 1 - trigger / lcd segment 9 / adc1_in19/ [comparator 1 positive input] 57 45 - pd4/tim1_ch2 /lcd_seg18 (3) / adc1_in10/ [comp1_inp] i/o ft (5) x xxhsxx port d4 timer 1 - channel 2 / lcd segment 18 / adc1_in10/ [comparator 1 positive input] --33 pd4/tim1_ch2 /lcd_seg18 (3) / adc1_in10/spi2_miso/ [comp1_inp] i/o ft (5) x xxhsxx port d4 timer 1 - channel 2 / lcd segment 18 / adc1_in10/spi2 master in/slave out/ [comparator 1 positive input] 58 46 - pd5/tim1_ch3 /lcd_seg19 (3) / adc1_in9/ [comp1_inp] i/o ft (5) x xxhsxx port d5 timer 1 - channel 3 / lcd segment 19 / adc1_in9/ [comparator 1 positive input] --34 pd5/tim1_ch3 /lcd_seg19 (3) / adc1_in9/spi2_mosi/ [comp1_inp] i/o ft (5) x xxhsxx port d5 timer 1 - channel 3 / lcd segment 19 / adc1_in9/ spi2 master out/slave in/ [comparator 1 positive input] 59 47 pd6/tim1_bkin /lcd_seg20 (3) / adc1_in8/rtc_calib/ [comp1_inp] /vrefint i/o ft (5) x xxhsxx port d6 timer 1 - break input / lcd segment 20 / adc1_in8 / rtc calibration/ [comparator 1 positive input] /internal reference voltage output --35 pd6/tim1_bkin /lcd_seg20 (3) / adc1_in8/rtc_calib/ spi2_sck/ [comp1_inp] / vrefint i/o ft (5) x xxhsxx port d6 timer 1 - break input / lcd segment 20 / adc1_in8 / rtc calibration/spi2 clock/ [comparator 1 positive input] /internal reference voltage output 60 48 - pd7/tim1_ch1n /lcd_seg21 (3) / adc1_in7/rtc_alarm/ [comp1_inp] /vrefint i/o ft (5) x xxhsxx port d7 timer 1 - inverted channel 1/ lcd segment 21 / adc1_in7 / rtc alarm/ [comparator 1 positive input] /internal reference voltage output table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 33/129 --36 pd7/tim1_ch1n /lcd_seg21 (3) / adc1_in7/rtc_alarm /spi2_nss/ [comp1_inp] / vrefint i/o ft (5) x xxhsxx port d7 timer 1 - inverted channel 1/ lcd segment 21 / adc1_in7 / rtc alarm /spi2 master/slave select/ [comparator 1 positive input] /internal reference voltage output 61 49 - pg4/lcd_seg32/ spi2_nss i/o ft (5) x xxhsxx port g4 lcd segment 32 / spi2 master/slave select 62 50 - pg5/lcd_seg33/ spi2_sck i/o ft (5) x xxhsxx port g5 lcd segment 33 / spi2 clock 63 51 - pg6/lcd_seg34/ spi2_mosi i/o ft (5) x xxhsxx port g6 lcd segment 34 / spi2 master out- slave in 64 52 - pg7/lcd_seg35/ spi2_miso i/o ft (5) x xxhsxx port g7 lcd segment 35 / spi2 master in- slave out 23 19 14 pe0/lcd_seg1 (3) / tim5_ch2 i/o ft (5) x xxhsxx port e0 lcd segment 1/ timer 5 channel 2 24 20 15 pe1/tim1_ch2n /lcd_seg2 (3) i/o ft (5) x xxhsxx port e1 timer 1 - inverted channel 2 / lcd segment 2 25 21 16 pe2/tim1_ch3n /lcd_seg3 (3) / [cco] (2) i/o ft (5) x xxhsxx port e2 timer 1 - inverted channel 3 / lcd segment 3 / [configurable clock output] 26 - - pe3/lcd_seg4 (3) i/o ft (5) x xxhsxx port e3 lcd segment 4 -2217 pe3/lcd_seg4 (3) / usart2_rx i/o ft (5) x xxhsxx port e3 lcd segment 4/ usart2 receive 27 - - pe4/lcd_seg5 (3) / dac_trig1 i/o ft (5) x xxhsxx port e4 lcd segment 5/ dac 1 trigger -2318 pe4/lcd_seg5 (3) / dac_trig2/usart2_tx i/o ft (5) x xxhsxx port e4 lcd segment 5/ dac 2 trigger/ usart2 transmit 28 - - pe5/lcd_seg6 (3) / adc1_in23/ [comp1_inp] / [comp2_inp] i/o ft (5) x xxhsxx port e5 lcd segment 6 / adc1_in23/ [comparator 1 positive input] / [comparator 2 positive input] table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp pin description stm8l15xx8, stm8l15xr6 34/129 doc id 17943 rev 5 -2419 pe5/lcd_seg6 (3) / adc1_in23/ [comp1_inp] / [comp2_inp] / usart2_ck i/o ft (5) x xxhsxx port e5 lcd segment 6 / adc1_in23/ [comparator 1 positive input] / [comparator 2 positive input] /usart2 synchronous clock --47 pe6/lcd_seg26 (3) / pvd_in/tim5_bkin/ usart3_tx/ [lcd_com6] (3) i/o ft (5) x xxhsxx port e6 lcd segment 26 /pvd_in /tim5 break input / usart3 transmit/ [lcd_com6] (3) 75 63 - pe6/lcd_seg26 (3) / pvd_in/tim5_bkin i/o ft (5) x xxhsxx port e6 lcd segment 26 /pvd_in /tim5 break input 76 64 - pe7/led_seg27/ tim5_etr i/o ft (5) x xxhsxx port e7 lcd segment 27/ tim5 trigger --48 pe7/led_seg27/ tim5_etr/usart3_rx/ [lcd_com7] (3) i/o ft (5) x xxhsxx port e7 lcd segment 27/ tim5 trigger/ usart3 receive/ [lcd_com7] (3) 77 - - pi0/rtc_tamp1/ [spi2_nss]/[tim3_ch3] i/o ft (5) x xhsxx port i0 rtc tamper 1 input [spi2 master/slave select] [tim3 channel 3] 78 - - pi1/rtc_tamp2/ [spi2_sck] i/o ft (5) x xhsxx port i1 rtc tamper 2 input [spi2 clock] 79 - - pi2/rtc_tamp3/ [spi2_mosi] i/o ft (5) x xhsxx port i2 rtc tamper 3 input [spi2 master out- slave in] 80 - - pi3/tim5_ch1/ [spi2_miso]/[tim3_ch2] i/o ft (5) x xhsxx port i3 tim5 channel 1 [spi2 master in- slave out] [tim3 channel 2] --32 pf0/adc1_in24/ dac_out1 i/o x xxhsxx port f0 adc1_in24 / dac 1 output -39- pf0/adc1_in24/ dac_out1/ [usart3_tx] i/o x xxhsxx port f0 adc1_in24 / dac 1 output/ [usart3 transmit] 49 - - pf0/adc1_in24/ dac_out1/ [usart3_tx]/[spi1_miso] i/o x xxhsxx port f0 adc1_in24 / dac 1 output/ [usart3 transmit] [spi1 master in- slave out ] table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 35/129 50 - - pf1/adc1_in25/ dac_out2/ [usart3_rx]/ [spi1_mosi] i/o x xxhsxx port f1 adc1_in25/ dac channel 2 output/ [usart3 receive] [spi1 master out- slave in ] -40- pf1/adc1_in25/ dac_out2/ [usart3_rx] i/o x xxhsxx port f1 adc1_in25/ dac channel 2 output/ [usart3 receive] 51 - - pf2/adc1_in26/ [spi2_sck] / [usart3_sck] i/o x xxhsxx port f2 adc1_in26 [spi2 clock] [usart3 clock] 52 - - pf3/adc1_in27/ [spi1_nss] i/o x xxhsxx port f3 adc1_in27 [spi1 master/slave select] 53 41 - pf4/lcd_seg36 / [lcd _com4] (9) i/o ft (5) x xxhsxx port f4 lcd segment 36/ [lcd_com4] (9) 54 42 - pf5/lcd_seg37 / [lcd_com5] (9) i/o ft (5) x xxhsxx port f5 lcd segment 37/ [lcd com5] (9) 55 43 - pf6/lcd_seg38 / [lcd_com6] (9) i/o ft (5) x xxhsxx port f6 lcd segment 38/ [lcd com6] (9) 56 44 - pf7/lcd_seg39 / [lcd_com7] (9) i/o ft (5) x xxhsxx port f7 lcd segment 39/ [ l cd com7] (9) 22 18 13 vlcd (7) s lcd booster external capacitor 15 11 10 v dd1 s digital power supply 14 10 - v ss1 i/o ground 16 12 11 v dda s analog supply voltage 17 13 12 v ref+/ v ref+_dac s adc1 and dac1/2 positive voltage reference 18 14 - pg0/lcd seg28 (3) /usart3_rx/ [tim2_bkin] i/o ft (5) x xxhsxx port g0 lcd segment 28/ usart3 receive / [timer 2 - break input] 19 15 - pg1/lcd seg29 (3) /usart3_tx/ [tim3_bkin] i/o ft (5) x xxhsxx port g1 lcd segment 29/ usart3 transmit / [timer 3 -break input] 20 16 - pg2/lcd_seg30 (3) / usart3_ck i/o ft (5) x xxhsxx port g2 lcd segment 30/ usart 3 synchronous clock table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp pin description stm8l15xx8, stm8l15xr6 36/129 doc id 17943 rev 5 21 17 - pg3/lcd seg 31 (3) / [tim3_etr] i/o ft (5) x xxhsxx port g3 lcd segment 31/ [timer 3 - trigger] 33 ph4/usart2_rx i/o ft (5) x xxhsxx port h4 usart2 receive 34 ph5/usart2_tx i/o ft (5) x xxhsxx port h5 usart2 transmit 35 ph6/usart2_ck/ tim5_ch1 i/o ft (5) x xxhsxx port h6 usart2 synchronous clock/ timer 5 - channel 1 36 ph7/tim5_ch2 i/o ft (5) x xxhsxx port h7 timer 5 - channel 2 -9v ss /v ssa/ v ref- s i/o ground / analog ground voltage / adc1 negative voltage reference 13 9 - v ssa/ v ref- s analog ground voltage / adc1 negative voltage reference 37 29 - v dd3 s ios supply voltage 38 30 - v ss3 s ios ground voltage 511 pa 0 (8) / [usart1_ck] (2) / swim/beep/ir_tim (9) i/o x x xhsx x port a0 [usart1 synchronous clock] (2) / swim input and output / beep output / infra- red timer output 68 56 40 v ss2 ios ground voltage 67 55 39 v dd2 ios supply voltage 48 - - v ss4 ios ground voltage 47 - - v dd4 ios supply voltage 1. at power-up, the pa1/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa1), it can be configured only as output pus h-pull, not as output open-drain nor as a general purpose input. refer to section configuring nrst/pa1 pin as general purpose output in the stm8l15xx and stm8l16xx reference manual (rm0031). 2. [ ] alternate function remapping option (if the same alternate function is shown twice, it i ndicates an exclusive choice not a duplication of the function). 3. available on stm8l152xx devices only. 4. a pull-up is applied to pb0 and pb4 during the reset phase . these two pins are input floating after reset release. 5. in the 5 v tolerant i/os, the protection diode to v dd is not implemented. 6. in the open-drain output column, ?t? de fines a true open-drain i/o (p -buffer, weak pull-up and protection diode to v dd are not implemented). 7. available on stm8l152xx devices only. on stm8l151x x devices it is reserved and must be tied to v dd . 8. the pa0 pin is in input pull-up during the reset phase and after reset release. 9. high sink led driver capability available on pa0. table 5. high density and medium+ density stm8l15x pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp80 lqfp64 ufqfpn48 and lqfp48 floating wpu ext. interrupt high sink/source od pp stm8l15xx8, stm8l15xr6 pin description doc id 17943 rev 5 37/129 note: slope control of all gpio pins can be programmed except true open drain pins and by default is limited to 2 mhz. system configuration options as shown in table 5: high density and medium+ density stm8l15x pin description , some alternate functions can be remapped on different i/o ports by programming one of the two remapping registers described in the ?routing interface (ri) and system configuration controller? section in the stm8l05xx, stm8l15xx and stm8l16xx reference manual (rm0031). memory and register map stm8l15xx8, stm8l15xr6 38/129 doc id 17943 rev 5 5 memory and register map 5.1 memory mapping the memory map is shown in figure 9 . figure 9. memory map 1. refer to table 9 for an overview of hardware register mapping, to table 8 for details on i/o port hardware registers, and to table 10 for information on cpu/swim/deb ug module controller registers. ' 0 ) / a n d p e r i p h e r a l r e g i s t e r s x ( i g h d e n s i t y u p t o + b y t e s 2 e s e t a n d i n t e r r u p t v e c t o r s x & & 2 ! - u p t o + b y t e s x & & & b y t e s x $ a t a % % 0 2 / - u p t o + b y t e s x x & & x x & & & x x & & & x x & & x % & & x x & x & 2 e s e r v e d 2 e s e r v e d i n c l u d i n g 3 t a c k / p t i o n b y t e s x & & & x x & & x 2 e s e r v e d x & & & " o o t 2 / - x x & & + b y t e s x 2 e s e r v e d # 0 5 3 7 ) - $ e b u g ) 4 # 2 e g i s t e r s x ' 0 ) / 0 o r t s x & l a s h x # ) 4 # % 8 4 ) x $ 2 3 4 x % # , + x & 7 7 $ ' x ) 7 $ ' x " % % 0 x 2 4 # x 3 0 ) x " ) # x % 5 3 ! 2 4 4 ) - 4 ) - 4 ) - 4 ) - ) 2 4 ) - ! $ # x $ - ! 3 9 3 # & ' $ ! # , # $ 2 ) x $ x ! x " x x x & & x x x x x # / - 0 & l a s h p r o g r a m m e m o r y 7 & % x ! x " 0 7 2 x x x x x x x 6 2 % & ) . 4 ? & a c t o r y ? # / . 6 4 3 ? & a c t o r y ? # / . 6 ? 6 x 2 e s e r v e d 5 n i q u e ) $ 2 e s e r v e d 4 ) - x x # 3 0 ) 5 3 ! 2 4 x % 5 3 ! 2 4 x & a i x stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 39/129 5.2 register map table 6. flash and ram boundary addresses memory area size start address end address ram 2 kbytes 0x00 0000 0x00 07ff 4 kbytes 0x00 0000 0x00 0fff flash program memory 32 kbytes 0x00 8000 0x00 ffff 64 kbytes 0x00 8000 0x01 7fff table 7. factory conversion registers address block register label register name reset status 0x00 4910 - vrefint_factory_ conv (1) internal reference voltage factory conversion 0xxx 0x00 4911 - ts_factory_conv_ v90 (2) temperature sensor output voltage 0xxx 1. the vrefint_factory_conv byte represents the 8 lsb of t he result of the vrefint 12-bi t adc conversion performed in factory. the 2 msb have a fixed value: 0x6. 2. the ts_factory_conv_v90 byte represents the 8 lsb of the result of the v90 12-bit adc conversion performed in factory. the 2 msb have a fixed value: 0x3. table 8. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x01 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 memory and register map stm8l15xx8, stm8l15xr6 40/129 doc id 17943 rev 5 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 0x00 501e port g pg_odr port f data output latch register 0x00 0x00 501f pg_idr port g input pin value register 0xxx 0x00 5020 pg_ddr port g data direction register 0x00 0x00 5021 pg_cr1 port g control register 1 0x00 0x00 5022 pg_cr2 port g control register 2 0x00 0x00 5023 port h ph_odr port h data output latch register 0x00 0x00 5024 ph_idr port h input pin value register 0xxx 0x00 5025 ph_ddr port h data direction register 0x00 0x00 5026 ph_cr1 port h control register 1 0x00 0x00 5027 ph_cr2 port h control register 2 0x00 0x00 5028 port i pi_odr port i data output latch register 0x00 0x00 5029 pi_idr port i input pin value register 0xxx 0x00 502a pi_ddr port i data direction register 0x00 0x00 502b pi_cr1 port i control register 1 0x00 0x00 502c pi_cr2 port i control register 2 0x00 table 8. i/o port hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 41/129 table 9. general hardware register map address block register label register name reset status 0x00 502e to 0x00 5049 reserved area (28 bytes) 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection key register 0x00 0x00 5053 flash _dukr data eeprom unprotection key register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0x00 0x00 5055 to 0x00 506f reserved area (27 bytes) 0x00 5070 dma1 dma1_gcsr dma1 global configuration & status register 0xfc 0x00 5071 dma1_gir1 dma1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 reserved area (3 bytes) 0x00 5075 dma1_c0cr dma1 channel 0 configuration register 0x00 0x00 5076 dma1_c0spr dma1 channel 0 status & priority register 0x00 0x00 5077 dma1_c0ndtr dma1 number of data to transfer register (channel 0) 0x00 0x00 5078 dma1_c0parh dma1 peripheral address high register (channel 0) 0x52 0x00 5079 dma1_c0parl dma1 peripheral address low register (channel 0) 0x00 0x00 507a reserved area (1 byte) 0x00 507b dma1_c0m0arh dma1 memory 0 address high register (channel 0) 0x00 0x00 507c dma1_c0m0arl dma1 memory 0 address low register (channel 0) 0x00 0x00 507d to 0x00 507e reserved area (2 bytes) 0x00 507f dma1_c1cr dma1 channel 1 configuration register 0x00 0x00 5080 dma1_c1spr dma1 channel 1 status & priority register 0x00 0x00 5081 dma1_c1ndtr dma1 number of data to transfer register (channel 1) 0x00 0x00 5082 dma1_c1parh dma1 peripheral address high register (channel 1) 0x52 memory and register map stm8l15xx8, stm8l15xr6 42/129 doc id 17943 rev 5 0x00 5083 dma1 dma1_c1parl dma1 peripheral address low register (channel 1) 0x00 0x00 5084 reserved area (1 byte) 0x00 5085 dma1 dma1_c1m0arh dma1 memory 0 address high register (channel 1) 0x00 0x00 5086 dma1_c1m0arl dma1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 reserved area (2 bytes) 0x00 5089 dma1 dma1_c2cr dma1 channel 2 c onfiguration register 0x00 0x00 508a dma1_c2spr dma1 channel 2 status & priority register 0x00 0x00 508b dma1_c2ndtr dma1 number of data to transfer register (channel 2) 0x00 0x00 508c dma1_c2parh dma1 peripheral address high register (channel 2) 0x52 0x00 508d dma1_c2parl dma1 peripheral address low register (channel 2) 0x00 0x00 508e reserved area (1 byte) 0x00 508f dma1_c2m0arh dma1 memory 0 address high register (channel 2) 0x00 0x00 5090 dma1_c2m0arl dma1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 reserved area (2 bytes) 0x00 5093 dma1 dma1_c3cr dma1 channel 3 c onfiguration register 0x00 0x00 5094 dma1_c3spr dma1 channel 3 status & priority register 0x00 0x00 5095 dma1_c3ndtr dma1 number of data to transfer register (channel 3) 0x00 0x00 5096 dma1_c3parh_ c3m1arh dma1 peripheral address high register (channel 3) 0x40 0x00 5097 dma1_c3parl_ c3m1arl dma1 peripheral address low register (channel 3) 0x00 0x00 5098 dma_c3m0ear dma channel 3 memory 0 extended address register 0x00 0x00 5099 dma1_c3m0arh dma1 memory 0 address high register (channel 3) 0x00 0x00 509a dma1_c3m0arl dma1 memory 0 address low register (channel 3) 0x00 0x00 509b to 0x00 509c reserved area (3 bytes) table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 43/129 0x00 509d syscfg syscfg_rmpcr3 remapping register 3 0x00 0x00 509e syscfg_rmpcr1 remapping register 1 0x00 0x00 509f syscfg_rmpcr2 remapping register 2 0x00 0x00 50a0 itc - exti exti_cr1 external interrup t control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf1 external interrupt port select register 1 0x00 0x00 50a6 wfe wfe_cr1 wfe control register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 wfe_cr3 wfe control register 3 0x00 0x00 50a9 wfe_cr4 wfe control register 4 0x00 0x00 50aa itc - exti exti_cr4 external interrup t control register 4 0x00 0x00 50ab exti_conf2 external interrupt port select register 2 0x00 0x00 50a9 to 0x00 50af reserved area (7 bytes) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 pwr pwr_csr1 power control and status register 1 0x00 0x00 50b3 pwr_csr2 power control and status register 2 0x00 0x00 50b4 to 0x00 50bf reserved area (12 bytes) 0x00 50c0 clk clk_ckdivr clock master divider register 0x03 0x00 50c1 clk_crtcr clock rtc register 0x00 (1) 0x00 50c2 clk_ickcr internal clock control register 0x11 0x00 50c3 clk_pckenr1 peripheral clock gating register 1 0x00 0x00 50c4 clk_pckenr2 peripheral clock gating register 2 0x00 0x00 50c5 clk_ccor configurable clock control register 0x00 0x00 50c6 clk_eckcr external clock control register 0x00 0x00 50c7 clk_scsr system clock status register 0x01 0x00 50c8 clk_swr system clock switch register 0x01 0x00 50c9 clk_swcr clock switch control register 0xx0 table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 44/129 doc id 17943 rev 5 0x00 50ca clk clk_cssr clock security system register 0x00 0x00 50cb clk_cbeepr clock beep register 0x00 0x00 50cc clk_hsicalr hsi calibration register 0xxx 0x00 50cd clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50ce clk_hsiunlckr hsi unlock register 0x00 0x00 50cf clk_regcsr main regulator co ntrol status register 0bxx11 100x 0x00 50d0 clk_pckenr3 peripheral clock gating register 3 0x00 0x00 50d1 to 0x00 50d2 reserved area (2 bytes) 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdr window register 0x7f 0x00 50d5 to 00 50df reserved area (11 bytes) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 bytes) 0x00 50f0 beep beep_csr1 beep control/status register 1 0x00 0x00 50f1 0x00 50f2 reserved area (2 bytes) 0x00 50f3 beep_csr2 beep control/status register 2 0x1f 0x00 50f4 to0x00 513f reserved area (76 bytes) 0x00 5140 rtc rtc_tr1 time register 1 0x00 0x00 5141 rtc_tr2 time register 2 0x00 0x00 5142 rtc_tr3 time register 3 0x00 0x00 5143 reserved area (1 byte) 0x00 5144 rtc rtc_dr1 date register 1 0x01 0x00 5145 rtc_dr2 date register 2 0x21 0x00 5146 rtc_dr3 date register 3 0x00 0x00 5147 reserved area (1 byte) table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 45/129 0x00 5148 rtc rtc_cr1 control register 1 0x00 (1) 0x00 5149 rtc_cr2 control register 2 0x00 (1) 0x00 514a rtc_cr3 control register 3 0x00 (1) 0x00 514b reserved area (1 byte) 0x00 514c rtc_isr1 initialization and status register 1 0x01 0x00 514d rtc_isr2 initialization and status register 2 0x00 0x00 514e 0x00 514f reserved area (2 bytes) 0x00 5150 rtc rtc_sprerh synchronous prescaler register high 0x00 (1) 0x00 5151 rtc_sprerl synchronous prescaler register low 0xff (1) 0x00 5152 rtc_aprer asynchronous prescaler register 0x7f (1) 0x00 5153 reserved area (1 byte) 0x00 5154 rtc rtc_wutrh wakeup timer register high 0xff (1) 0x00 5155 rtc_wutrl wakeup timer register low 0xff (1) 0x00 5156 reserved area (1 byte) 0x00 5157 rtc rtc_ssrl subsecond register low 0x00 0x00 5158 rtc_ssrh subsecond register high 0x00 0x00 5159 rtc_wpr write protection register 0x00 0x00 5158 rtc_ssrh subsecond register high 0x00 0x00 5159 rtc_wpr write protection register 0x00 0x00 515a rtc_shiftrh shift register high 0x00 0x00 515b rtc_shiftrl shift register low 0x00 0x00 515c rtc_alrmar1 alarm a register 1 0x00 (1) 0x00 515d rtc_alrmar2 alarm a register 2 0x00 (1) 0x00 515e rtc_alrmar3 alarm a register 3 0x00 (1) 0x00 515f rtc_alrmar4 alarm a register 4 0x00 (1) 0x00 5160 to 0x00 5163 reserved area (4 bytes) 0x00 5164 rtc rtc_alrmassrh alarm a subsec ond register high 0x00 (1) 0x00 5165 rtc_alrmassrl alarm a subsecond register low 0x00 (1) 0x00 5166 rtc_alrmassms kr alarm a masking register 0x00 (1) 0x00 5167 to 0x00 5169 reserved area (3 bytes) table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 46/129 doc id 17943 rev 5 0x00 516a rtc rtc_calrh calibration register high 0x00 (1) 0x00 516b rtc_calrl calibration register low 0x00 (1) 0x00 516c rtc_tcr1 tamper control register 1 0x00 (1) 0x00 516d rtc_tcr2 tamper control register 2 0x00 (1) 0x00 516e to 0x00 518a reserved area 0x00 5190 csslse csslse_csr css on lse control and status register 0x00 (1) 0x00 519a to 0x00 51ff reserved area 0x00 5200 spi1 spi1_cr1 spi1 control register 1 0x00 0x00 5201 spi1_cr2 spi1 control register 2 0x00 0x00 5202 spi1_icr spi1 inte rrupt control register 0x00 0x00 5203 spi1_sr spi1 status register 0x02 0x00 5204 spi1_dr spi1 data register 0x00 0x00 5205 spi1_crcpr spi1 crc polynomial register 0x07 0x00 5206 spi1_rxcrcr spi1 rx crc register 0x00 0x00 5207 spi1_txcrcr spi1 tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 bytes) 0x00 5210 i2c1 i2c1_cr1 i2c1 control register 1 0x00 0x00 5211 i2c1_cr2 i2c1 control register 2 0x00 0x00 5212 i2c1_freqr i2c1 frequency register 0x00 0x00 5213 i2c1_oarl i2c1 own address register low 0x00 0x00 5214 i2c1_oarh i2c1 own address register high 0x00 0x00 5215 i2c1_oarh i2c1 own address register for dual mode 0x00 0x00 5216 i2c1_dr i2c1 data register 0x00 0x00 5217 i2c1_sr1 i2c1 status register 1 0x00 0x00 5218 i2c1_sr2 i2c1 status register 2 0x00 0x00 5219 i2c1_sr3 i2c1 status register 3 0x0x 0x00 521a i2c1_itr i2c1 interrupt control register 0x00 0x00 521b i2c1_ccrl i2c1 clock control register low 0x00 0x00 521c i2c1_ccrh i2c1 clock control register high 0x00 0x00 521d i2c1_triser i2c1 trise register 0x02 0x00 521e i2c1_pecr i2c1 packet error checking register 0x00 table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 47/129 0x00 521f to 0x00 522f reserved area (17 bytes) 0x00 5230 usart1 usart1_sr usart1 status register 0xc0 0x00 5231 usart1_dr usart1 data register 0xxx 0x00 5232 usart1_brr1 usart1 baud rate register 1 0x00 0x00 5233 usart1_brr2 usart1 baud rate register 2 0x00 0x00 5234 usart1_cr1 usart1 control register 1 0x00 0x00 5235 usart1_cr2 usart1 control register 2 0x00 0x00 5236 usart1_cr3 usart1 control register 3 0x00 0x00 5237 usart1_cr4 usart1 control register 4 0x00 0x00 5238 usart1_cr5 usart1 control register 5 0x00 0x00 5239 usart1_gtr usart1 guard time register 0x00 0x00 523a usart1_pscr usart1 prescaler register 0x00 0x00 523b to 0x00 524f reserved area (21 bytes) 0x00 5250 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slav e mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_der tim2 dma1 request enable register 0x00 0x00 5255 tim2_ier tim2 interrupt enable register 0x00 0x00 5256 tim2_sr1 tim2 status register 1 0x00 0x00 5257 tim2_sr2 tim2 status register 2 0x00 0x00 5258 tim2_egr tim2 event generation register 0x00 0x00 5259 tim2_ccmr1 tim2 capture/compare mode register 1 0x00 0x00 525a tim2_ccmr2 tim2 capture/compare mode register 2 0x00 0x00 525b tim2_ccer1 tim2 capture/compare enable register 1 0x00 0x00 525c tim2_cntrh tim2 counter high 0x00 0x00 525d tim2_cntrl ti m2 counter low 0x00 0x00 525e tim2_pscr tim2 prescaler register 0x00 0x00 525f tim2_arrh tim2 auto-reload register high 0xff 0x00 5260 tim2_arrl tim2 auto-reload register low 0xff 0x00 5261 tim2_ccr1h tim2 captur e/compare register 1 high 0x00 table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 48/129 doc id 17943 rev 5 0x00 5262 tim2 tim2_ccr1l tim2 capture/co mpare register 1 low 0x00 0x00 5263 tim2_ccr2h tim2 captur e/compare register 2 high 0x00 0x00 5264 tim2_ccr2l tim2 captur e/compare register 2 low 0x00 0x00 5265 tim2_bkr tim2 break register 0x00 0x00 5266 tim2_oisr tim2 output idle state register 0x00 0x00 5267 to 0x00 527f reserved area (25 bytes) 0x00 5280 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slav e mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_der tim3 dma1 request enable register 0x00 0x00 5285 tim3_ier tim3 interrupt enable register 0x00 0x00 5286 tim3_sr1 tim3 status register 1 0x00 0x00 5287 tim3_sr2 tim3 status register 2 0x00 0x00 5288 tim3_egr tim3 event generation register 0x00 0x00 5289 tim3_ccmr1 tim3 capture/compare mode register 1 0x00 0x00 528a tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 528b tim3_ccer1 tim3 capture/compare enable register 1 0x00 0x00 528c tim3_cntrh tim3 counter high 0x00 0x00 528d tim3_cntrl ti m3 counter low 0x00 0x00 528e tim3_pscr tim3 prescaler register 0x00 0x00 528f tim3_arrh tim3 auto-reload register high 0xff 0x00 5290 tim3_arrl tim3 auto-reload register low 0xff 0x00 5291 tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 5292 tim3_ccr1l tim3 capture/compare register 1 low 0x00 0x00 5293 tim3_ccr2h tim3 captur e/compare register 2 high 0x00 0x00 5294 tim3_ccr2l tim3 capture/compare register 2 low 0x00 0x00 5295 tim3_bkr tim3 break register 0x00 0x00 5296 tim3_oisr tim3 output idle state register 0x00 0x00 5297 to 0x00 52af reserved area (25 bytes) table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 49/129 0x00 52b0 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 52b1 tim1_cr2 tim1 control register 2 0x00 0x00 52b2 tim1_smcr tim1 slave mode control register 0x00 0x00 52b3 tim1_etr tim1 external trigger register 0x00 0x00 52b4 tim1_der tim1 dma1 request enable register 0x00 0x00 52b5 tim1_ier tim1 interr upt enable register 0x00 0x00 52b6 tim1_sr1 tim1 st atus register 1 0x00 0x00 52b7 tim1_sr2 tim1 st atus register 2 0x00 0x00 52b8 tim1_egr tim1 event generation register 0x00 0x00 52b9 tim1_ccmr1 tim1 capture/compare mode register 1 0x00 0x00 52ba tim1_ccmr2 tim1 capture/compare mode register 2 0x00 0x00 52bb tim1_ccmr3 tim1 capture/compare mode register 3 0x00 0x00 52bc tim1_ccmr4 tim1 capture/compare mode register 4 0x00 0x00 52bd tim1_ccer1 tim1 capture/compare enable register 1 0x00 0x00 52be tim1_ccer2 tim1 capture/compare enable register 2 0x00 0x00 52bf tim1_cntrh tim1 counter high 0x00 0x00 52c0 tim1_cntrl ti m1 counter low 0x00 0x00 52c1 tim1_pscrh tim1 prescaler register high 0x00 0x00 52c2 tim1_pscrl tim1 prescaler register low 0x00 0x00 52c3 tim1_arrh tim1 auto-reload register high 0xff 0x00 52c4 tim1_arrl tim1 auto-reload register low 0xff 0x00 52c5 tim1_rcr tim1 repetition counter register 0x00 0x00 52c6 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 52c7 tim1_ccr1l tim1 capture/compare register 1 low 0x00 0x00 52c8 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 52c9 tim1_ccr2l tim1 capture/compare register 2 low 0x00 0x00 52ca tim1_ccr3h tim1 capture/ compare register 3 high 0x00 0x00 52cb tim1_ccr3l tim1 capture/compare register 3 low 0x00 0x00 52cc tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 52cd tim1_ccr4l tim1 capture/compare register 4 low 0x00 0x00 52ce tim1_bkr tim1 break register 0x00 0x00 52cf tim1_dtr tim1 dead-time register 0x00 0x00 52d0 tim1_oisr tim1 output idle state register 0x00 0x00 52d1 tim1_dcr1 dma1 control register 1 0x00 table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 50/129 doc id 17943 rev 5 0x00 52d2 tim1 tim1_dcr2 tim1 dma1 control register 2 0x00 0x00 52d3 tim1_dma1r tim1 dma1 address for burst mode 0x00 0x00 52d4 to 0x00 52df reserved area (12 bytes) 0x00 52e0 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_der tim4 dma1 request enable register 0x00 0x00 52e4 tim4_ier tim4 interr upt enable register 0x00 0x00 52e5 tim4_sr1 tim4 st atus register 1 0x00 0x00 52e6 tim4_egr tim4 event generation register 0x00 0x00 52e7 tim4_cntr tim4 counter 0x00 0x00 52e8 tim4_pscr tim4 prescaler register 0x00 0x00 52e9 tim4_arr tim4 auto-reload register 0x00 0x00 52ea to 0x00 52fe reserved area (21 bytes) 0x00 52ff irtim ir_cr infrared control register 0x00 0x00 5300 tim5 tim5_cr1 tim5 control register 1 0x00 0x00 5301 tim5_cr2 tim5 control register 2 0x00 0x00 5302 tim5_smcr tim5 slav e mode control register 0x00 0x00 5303 tim5_etr tim5 external trigger register 0x00 0x00 5304 tim5_der tim5 dma1 request enable register 0x00 0x00 5305 tim5_ier tim5 interrupt enable register 0x00 0x00 5306 tim5_sr1 tim5 status register 1 0x00 0x00 5307 tim5_sr2 tim5 status register 2 0x00 0x00 5308 tim5_egr tim5 event generation register 0x00 0x00 5309 tim5_ccmr1 tim5 capture/compare mode register 1 0x00 0x00 530a tim5_ccmr2 tim5 capture/compare mode register 2 0x00 0x00 530b tim5_ccer1 tim5 capture/compare enable register 1 0x00 0x00 530c tim5_cntrh tim5 counter high 0x00 0x00 530d tim5_cntrl ti m5 counter low 0x00 0x00 530e tim5_pscr tim5 prescaler register 0x00 0x00 530f tim5_arrh tim5 auto-reload register high 0xff table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 51/129 0x00 5310 tim5 tim5_arrl tim5 auto-reload register low 0xff 0x00 5311 tim5_ccr1h tim5 captur e/compare register 1 high 0x00 0x00 5312 tim5_ccr1l tim5 capture/compare register 1 low 0x00 0x00 5313 tim5_ccr2h tim5 captur e/compare register 2 high 0x00 0x00 5314 tim5_ccr2l tim5 capture/compare register 2 low 0x00 0x00 5315 tim5_bkr tim5 break register 0x00 0x00 5316 tim5_oisr tim5 output idle state register 0x00 0x00 5317 to 0x00 533f reserved area 0x00 5340 adc1 adc1_cr1 adc1 configuration register 1 0x00 0x00 5341 adc1_cr2 adc1 configuration register 2 0x00 0x00 5342 adc1_cr3 adc1 configuration register 3 0x1f 0x00 5343 adc1_sr adc1 status register 0x00 0x00 5344 adc1_drh adc1 data register high 0x00 0x00 5345 adc1_drl adc1 data register low 0x00 0x00 5346 adc1_htrh adc1 high threshold register high 0x0f 0x00 5347 adc1_htrl adc1 high threshold register low 0xff 0x00 5348 adc1_ltrh adc1 low threshold register high 0x00 0x00 5349 adc1_ltrl adc1 low threshold register low 0x00 0x00 534a adc1_sqr1 adc1 channel sequence 1 register 0x00 0x00 534b adc1_sqr2 adc1 channel sequence 2 register 0x00 0x00 534c adc1_sqr3 adc1 channel sequence 3 register 0x00 0x00 534d adc1_sqr4 adc1 channel sequence 4 register 0x00 0x00 534e adc1_trigr1 adc1 trigger disable 1 0x00 0x00 534f adc1_trigr2 adc1 trigger disable 2 0x00 0x00 5350 adc1_trigr3 adc1 trigger disable 3 0x00 0x00 5351 adc1_trigr4 adc1 trigger disable 4 0x00 0x00 5352 to 0x00 537f reserved area (46 bytes) table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 52/129 doc id 17943 rev 5 0x00 5380 dac dac_ch1cr1 dac channel 1 control register 1 0x00 0x00 5381 dac_ch1cr2 dac channel 1 control register 2 0x00 0x00 5382 dac_ch2cr1 dac channel 2 control register 1 0x00 0x00 5383 dac_ch2cr2 dac channel 2 control register 2 0x00 0x00 5384 dac_swtrig dac software trigger register 0x00 0x00 5385 dac_sr dac status register 0x00 0x00 5386 to 0x00 5387 reserved area (2 bytes) 0x00 5388 dac dac_ch1rdhrh dac channel 1 right aligned data holding register high 0x00 0x00 5389 dac_ch1rdhrl dac channel 1 right aligned data holding register low 0x00 0x00 538a to 0x00 538b reserved area (2 bytes) 0x00 538c dac dac_ch1ldhrh dac channel 1 left aligned data holding register high 0x00 0x00 538d dac dac_ch1ldhrl dac channel 1 left aligned data holding register low 0x00 0x00 538e to 0x00 538f reserved area (2 bytes) 0x00 5390 dac dac_ch1dhr8 dac channel 1 8-bit data holding register 0x00 0x00 5391 to 0x00 5393 reserved area (3 bytes) 0x00 5394 dac dac_ch2rdhrh dac channel 2 right aligned data holding register high 0x00 0x00 5395 dac_ch2rdhrl dac channel 2 right aligned data holding register low 0x00 0x00 5396 to 0x00 5397 reserved area (2 bytes) 0x00 5398 dac dac_ch2ldhrh dac channel 2 left aligned data holding register high 0x00 0x00 5399 dac_ch2ldhrl dac channel 2 left aligned data holding register low 0x00 0x00 539a to 0x00 539b reserved area (2 bytes) 0x00 539c dac dac_ch2dhr8 dac channel 2 8-bit data holding register 0x00 0x00 539d to 0x00 539f reserved area (3 bytes) table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 53/129 0x00 53a0 dac dac_dch1rdhrh dac channel 1 right aligned data holding register high 0x00 0x00 53a1 dac_dch1rdhrl dac channel 1 right aligned data holding register low 0x00 0x00 53a2 to 0x00 53ab reserved area (3 bytes) 0x00 53ac dac dac_dorh dac data output register high 0x00 0x00 53ad dac_dorl dac data output register low 0x00 0x00 53a2 dac_dch2rdhrh dac channel 2 right aligned data holding register high 0x00 0x00 53a3 dac_dch2rdhrl dac channel 2 right aligned data holding register low 0x00 0x00 53a4 dac_dch1ldhrh dac channel 1left aligned data holding register high 0x00 0x00 53a5 dac_dch1ldhrl dac channel 1left aligned data holding register low 0x00 0x00 53a6 dac_dch2ldhrh dac channel 2 left aligned data holding register high 0x00 0x00 53a7 dac_dch2ldhrl dac channel 2 left aligned data holding register low 0x00 0x00 53a8 dac_dch1dhr8 dac channel 1 8-bit mode data holding register 0x00 0x00 53a9 dac_dch2dhr8 dac channel 2 8-bit mode data holding register 0x00 0x00 53aa to 0x00 53ab reserved area (2 bytes) 0x00 53ac dac dac_ch1dorh reset value dac channel 1 data output register high 0x00 0x00 53ad dac_ch1dorl reset value dac channel 1 data output register low 0x00 0x00 53ae to 0x00 53af reserved area (2 bytes) 0x00 53b0 dac dac_ch2dorh reset value dac channel 2 data output register high 0x00 0x00 53b1 dac_ch2dorl reset value dac channel 2 data output register low 0x00 0x00 53b2 to 0x00 53bf reserved area table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 54/129 doc id 17943 rev 5 0x00 53c0 spi2 spi2_cr1 spi2 control register 1 0x00 0x00 53c1 spi2_cr2 spi2 control register 2 0x00 0x00 53c2 spi2_icr spi2 interr upt control register 0x00 0x00 53c3 spi2_sr spi2 status register 0x02 0x00 53c4 spi2_dr spi2 data register 0x00 0x00 53c5 spi2_crcpr spi2 crc polynomial register 0x07 0x00 53c6 spi2_rxcrcr spi2 rx crc register 0x00 0x00 53c7 spi2_txcrcr spi2 tx crc register 0x00 0x00 53c8 to 0x00 53df reserved area 0x00 53e0 usart2 usart2_sr usart2 status register 0xc0 0x00 53e1 usart2_dr usart2 data register 0xxx 0x00 53e2 usart2_brr1 usart2 baud rate register 1 0x00 0x00 53e3 usart2_brr2 usart2 baud rate register 2 0x00 0x00 53e4 usart2_cr1 usart2 control register 1 0x00 0x00 53e5 usart2_cr2 usart2 control register 2 0x00 0x00 53e6 usart2_cr3 usart2 control register 3 0x00 0x00 53e7 usart2_cr4 usart2 control register 4 0x00 0x00 53e8 usart2_cr5 usart2 control register 5 0x00 0x00 53e9 usart2_gtr usart2 guard time register 0x00 0x00 53ea usart2_pscr usart2 prescaler register 0x00 0x00 53eb to 0x00 53ef reserved area 0x00 53f0 usart3 usart3_sr usart3 status register 0xc0 0x00 53f1 usart3_dr usar t3 data register 0xxx 0x00 53f2 usart3_brr1 usart3 baud rate register 1 0x00 0x00 53f3 usart3_brr2 usart3 baud rate register 2 0x00 0x00 53f4 usart3_cr1 usart3 control register 1 0x00 0x00 53f5 usart3_cr2 usart3 control register 2 0x00 0x00 53f6 usart3_cr3 usart3 control register 3 0x00 0x00 53f7 usart3_cr4 usart3 control register 4 0x00 0x00 53f8 usart3_cr5 usart3 control register 5 0x00 0x00 53f9 usart3_gtr usart3 guard time register 0x00 0x00 53fa usart3_pscr usart3 prescaler register 0x00 table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 55/129 0x00 53fb to 0x00 53ff reserved area 0x00 5400 lcd lcd_cr1 lcd control register 1 0x00 0x00 5401 lcd_cr2 lcd control register 2 0x00 0x00 5402 lcd_cr3 lcd control register 3 0x00 0x00 5403 lcd_frq lcd frequency selection register 0x00 0x00 5404 lcd_pm0 lcd port mask register 0 0x00 0x00 5405 lcd_pm1 lcd port mask register 1 0x00 0x00 5406 lcd_pm2 lcd port mask register 2 0x00 0x00 5407 lcd_pm3 lcd port mask register 3 0x00 0x00 5408 lcd_pm4 lcd port mask register 4 0x00 0x00 5409 lcd_pm5 lcd port mask register 5 0x00 0x00 540a to 0x00 540b reserved area (2 bytes) 0x00 540c lcd lcd_ram0 lcd display memory 0 0x00 0x00 540d lcd_ram1 lcd display memory 1 0x00 0x00 540e lcd_ram2 lcd display memory 2 0x00 0x00 540f lcd_ram3 lcd display memory 3 0x00 0x00 5410 lcd_ram4 lcd display memory 4 0x00 0x00 5411 lcd_ram5 lcd display memory 5 0x00 0x00 5412 lcd_ram6 lcd display memory 6 0x00 0x00 5413 lcd_ram7 lcd display memory 7 0x00 0x00 5414 lcd_ram8 lcd display memory 8 0x00 0x00 5415 lcd_ram9 lcd display memory 9 0x00 0x00 5416 lcd_ram10 lcd display memory 10 0x00 0x00 5417 lcd_ram11 lcd display memory 11 0x00 0x00 5418 lcd_ram12 lcd display memory 12 0x00 0x00 5419 lcd_ram13 lcd display memory 13 0x00 0x00 541a lcd_ram14 lcd display memory 14 0x00 0x00 541b lcd_ram15 lcd display memory 15 0x00 0x00 541c lcd_ram16 lcd display memory 16 0x00 0x00 541d lcd_ram17 lcd display memory 17 0x00 0x00 541e lcd_ram18 lcd display memory 18 0x00 0x00 541f lcd_ram19 lcd display memory 19 0x00 0x00 5420 lcd_ram20 lcd display memory 20 0x00 table 9. general hardware register map (continued) address block register label register name reset status memory and register map stm8l15xx8, stm8l15xr6 56/129 doc id 17943 rev 5 0x00 5421 lcd lcd_ram21 lcd display memory 21 0x00 0x00 5422 to 0x00 542e reserved area 0x00 542f lcd lcd_cr4 lcd control register 4 0x00 0x00 5430 ri reserved area (1 byte) 0x00 0x00 5431 ri_icr1 timer input c apture routing register 1 0x00 0x00 5432 ri_icr2 timer input c apture routing register 2 0x00 0x00 5433 ri_ioir1 i/o input register 1 0xxx 0x00 5434 ri_ioir2 i/o input register 2 0xxx 0x00 5435 ri_ioir3 i/o input register 3 0xxx 0x00 5436 ri_iocmr1 i/o control mode register 1 0x00 0x00 5437 ri_iocmr2 i/o control mode register 2 0x00 0x00 5438 ri_iocmr3 i/o control mode register 3 0x00 0x00 5439 ri_iosr1 i/o switch register 1 0x00 0x00 543a ri_iosr2 i/o switch register 2 0x00 0x00 543b ri_iosr3 i/o switch register 3 0x00 0x00 543c ri_iogcr i/o group control register 0x3f 0x00 543d ri_ascr1 analog switch register 1 0x00 0x00 543e ri_ascr2 analog switch register 2 0x00 0x00 543f ri_rcr resistor control register 1 0x00 0x00 5440 comp1/ comp2 comp_csr1 comparator control and status register 1 0x00 0x00 5441 comp_csr2 comparator control and status register 2 0x00 0x00 5442 comp_csr3 comparator control and status register 3 0x00 0x00 5443 comp_csr4 comparator control and status register 4 0x00 0x00 5444 comp_csr5 comparator control and status register 5 0x00 1. these registers are not impacted by a sy stem reset. they are reset at power-on. table 9. general hardware register map (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 memory and register map doc id 17943 rev 5 57/129 table 10. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 bytes) 0x00 7f60 cpu cfg_gcr global configuration register 0x00 0x00 7f70 itc-spr itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 bytes) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 bytes) memory and register map stm8l15xx8, stm8l15xr6 58/129 doc id 17943 rev 5 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 bytes) 1. accessible by debug module only table 10. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status stm8l15xx8, stm8l15xr6 interrupt vector mapping doc id 17943 rev 5 59/129 6 interrupt vector mapping table 11. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address reset reset yes yes yes yes 0x00 8000 trap software interrupt - - - - 0x00 8004 0tli (2) external top level interrupt - - - - 0x00 8008 1 flash eop/wr_pg_dis - - yes yes (3) 0x00 800c 2 dma1 0/1 dma1 channels 0/1 - - yes yes (3) 0x00 8010 3 dma1 2/3 dma1 channels 2/3 - - yes yes (3) 0x00 8014 4 rtc/lse_ css rtc alarm interrupt/lse css interrupt yes yes yes yes 0x00 8018 5 exti e/f/pvd (4) porte/f interrupt/pvd interrupt ye s ye s ye s ye s (3) 0x00 801c 6 extib/g external interrupt port b/g yes yes yes yes (3) 0x00 8020 7 extid/h external interrupt port d/h yes yes yes yes (3) 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes (3) 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes (3) 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes (3) 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes (3) 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes (3) 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes (3) 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes (3) 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes (3) 0x00 8044 16 lcd lcd interrupt - - yes yes 0x00 8048 17 clk/ tim1/ dac system clock switch/css interrupt/tim1 break/dac - - yes yes 0x00 804c 18 comp1/ comp2 adc1 comparator 1 and 2 interrupt/adc1 ye s ye s ye s ye s (3) 0x00 8050 19 tim2/ usart2 tim2 update /overflow/trigger/break/ usart2 transmission complete/transmit data register empty interrupt --yesyes (3) 0x00 8054 interrupt vector mapping stm8l15xx8, stm8l15xr6 60/129 doc id 17943 rev 5 20 tim2/ usart2 capture/compare/usart 2 interrupt --yesyes (3) 0x00 8058 21 tim3/ usart3 tim3 update /overflow/trigger/break/ usart3 transmission complete/transmit data register empty interrupt --yesyes (3) 0x00 805c 22 tim3/ usart3 tim3 capture/compare/ usart3 receive register data full/overrun/idle line detected/parity error/ interrupt --yesyes (3) 0x00 8060 23 tim1 update /overflow/trigger/ com ---yes (3) 0x00 8064 24 tim1 capture/compare - - - yes (3) 0x00 8068 25 tim4 update/overflow/trigger - - yes yes (3) 0x00 806c 26 spi1 end of transfer yes yes yes yes (3) 0x00 8070 27 usart 1/ tim5 usart1 transmission complete/transmit data register empty/ tim5 update/overflow/ trigger/break --yesyes (3) 0x00 8074 28 usart 1/ tim5 usart1 receive register data full/overrun/idle line detected/parity error/ tim5 capture/compare --yesyes (3) 0x00 8078 29 i 2 c1/spi2 i 2 c1 interrupt (5) / spi2 ye s ye s ye s ye s (3) 0x00 807c 1. the low power wait mode is entered when executing a wfe instruction in low power run mode. 2. the tli interrupt is the logic or between tim2 overflow interrupt, and tim4 overflow interrupts. 3. in wfe mode, this interrupt is served if it has been previ ously enabled. after processing t he interrupt, the processor goes back to wfe mode. when this interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. 4. the interrupt from pvd is logically or-ed with port e and f in terrupts. register exti_conf allows to select between port e and port f interrupt (see external interrupt port sele ct register (exti_conf) in the rm0031). 5. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 11. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address stm8l15xx8, stm8l15xr6 option bytes doc id 17943 rev 5 61/129 7 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated memory block. all option bytes can be modified in icp mode (with swim) by accessing the eeprom address. see ta b l e 1 2 for details on option byte addresses. the option bytes can also be modified ?on the fly? by the application in iap mode, except for the rop, ubc and pcodesize values which can only be taken into account when they are modified in icp mode (with the swim). refer to the stm8l15x/stm8l16x flash programming manual (pm0054) and stm8 swim and debug manual (um0470) for information on swim programming procedures. table 12. option byte addresses address option name option byte no. option bits factory default setting 7654 3 2 1 0 00 4800 read-out protection (rop) opt0 rop[7:0] 0xaa 00 4802 ubc (user boot code size) opt1 ubc[7:0] 0x00 00 4807 pcodesize opt2 pcode[7:0] 0x00 00 4808 independent watchdog option opt3 [3:0] reserved wwdg _halt wwdg _hw iwdg _halt iwdg _hw 0x00 00 4809 number of stabilization clock cycles for hse and lse oscillators opt4 reserved lsecnt[1:0] hsecnt[1:0] 0x00 00 480a brownout reset (bor) opt5 [3:0] reserved bor_th bor_ on 0x00 00 480b bootloader option bytes (optbl) optbl [15:0] optbl[15:0] 0x00 00 480c 0x00 option bytes stm8l15xx8, stm8l15xr6 62/129 doc id 17943 rev 5 table 13. option byte description option byte no. option description opt0 rop[7:0] memory readout protection (rop) 0xaa: disable readout protection (write access via swim protocol) refer to readout protection section in the stm8l reference manual (rm0031). opt1 ubc[7:0] size of the user boot code area ubc[7:0] size of the user boot code area 0x00: no ubc 0x01: page 0 reserved for the ubc and write protected. ... 0xff: page 0 to 254 reserved for the ubc and write-protected. refer to user boot code section in the stm8l reference manual (rm0031). opt2 pcodesize[7:0] size of the proprietary code area 0x00: no proprietary code area 0x01: page 0 reserved for the proprietary code and read/write protected. ... 0xff: page 0 to 254 reserved for the proprietary code and read/write protected. refer to proprietary code area (pcode) section in the stm8l reference manual (rm0031) for more details. opt3 iwdg_hw: independent watchdog 0: independent watchdog activated by software 1: independent watchdog activated by hardware iwdg_halt: independent watchdog off in halt/active-halt 0: independent watchdog continues running in halt/active-halt mode 1: independent watchdog stopped in halt/active-halt mode wwdg_hw: window watchdog 0: window watchdog activated by software 1: window watchdog activated by hardware wwdg_halt: window window watchdog reset on halt/active-halt 0: window watchdog stopped in halt mode 1: window watchdog generates a reset when mcu enters halt mode opt4 hsecnt : number of hse oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles lsecnt : number of lse oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles stm8l15xx8, stm8l15xr6 option bytes doc id 17943 rev 5 63/129 opt5 bor_on : 0: brownout reset off 1: brownout reset on bor_th[3:1] : brownout reset thresholds. refer to ta b l e 2 0 for details on the thresholds according to the value of bor_th bits. optbl optbl[15:0] : this option is checked by the boot rom code after reset. depending on the content of addresses 00 480b, 00 480c and 0x8000 (reset vector) the cpu jumps to the bootloader or to the reset vector. refer to the um0560 bootloader user manual for more details. table 13. option byte description (continued) option byte no. option description unique id stm8l15xx8, stm8l15xr6 64/129 doc id 17943 rev 5 8 unique id stm8 devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any contex t. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: for use as serial numbers for use as security keys to increase the code security in the program memory while using and combining this un ique id with software cryp tographic primitives and protocols before programming the internal memory. to activate secure boot processes table 14. unique id registers (96 bits) address content description unique id bits 7654 3 2 1 0 0x4926 x co-ordinate on the wafer u_id[7:0] 0x4927 u_id[15:8] 0x4928 y co-ordinate on the wafer u_id[23:16] 0x4929 u_id[31:24] 0x492a wafer number u_id[39:32] 0x492b lot number u_id[47:40] 0x492c u_id[55:48] 0x492d u_id[63:56] 0x492e u_id[71:64] 0x492f u_id[79:72] 0x4930 u_id[87:80] 0x4931 u_id[95:88] stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 65/129 9 electrical parameters 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 9.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 10 . figure 10. pin loading conditions 50 pf stm8l pin electrical parameters stm8l15xx8, stm8l15xr6 66/129 doc id 17943 rev 5 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 11 . figure 11. pin input voltage 9.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. v in stm8l pin table 15. voltage characteristics symbol ratings min max unit v dd - v ss external supply voltage (including v dda ) (1) 1. all power (v dd1 , v dd2 , v dd3 , v dd4 , v dda ) and ground (v ss1 , v ss2 , v ss3 , v ss4 , v ssa ) pins must always be connected to the external power supply. - 0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 16. for maximum allowed injected current values. input voltage on true open-drain pins (pc0 and pc1) v ss - 0.3 v dd + 4.0 input voltage on five-volt tolerant (ft) pins v ss - 0.3 v dd + 4.0 input voltage on any other pin v ss - 0.3 4.0 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 119 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 67/129 table 16. current characteristics symbol ratings max. unit i vdd total current into v dd power line (source) 80 ma i vss total current out of v ss ground line (sink) 80 i io output current sunk by ir_tim pin (with high sink led driver capability) 80 output current sunk by any other i/o and control pin 25 output current sourced by any i/os and control pin - 25 i inj(pin) injected current on true open-drain pins (pc0 and pc1) (1) - 5 / +0 injected current on five-volt tolerant (ft) pins (1) 1. positive injection is not possible on thes e i/os. a negative injection is induced by v in stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 69/129 9.3.2 embedded reset and power control block characteristics table 19. embedded reset and power control block characteristics symbol parameter conditions min. typ. max. unit t vdd v dd rise time rate bor detector enabled 0 (1) (1) s/v bor detector disabled 0 (1) 1 (1) ms/v v dd fall time rate bor detector enabled 20 (1) (1) s/v bor detector disabled reset below voltage functional range t temp reset release delay v dd rising bor detector enabled 3 ms v dd rising bor detector disabled 1 v por power-on reset threshold rising edge 1.3 (2) 1.5 1.65 v v pdr power-down reset threshold falling edge 1.3 (2) 1.5 1.65 v bor0 brown-out reset threshold 0 (bor_th[2:0]=000) falling edge 1.67 1.7 1.74 rising edge 1.69 1.75 1.80 v bor1 brown-out reset threshold 1 (bor_th[2:0]=001) falling edge 1.87 1.93 1.97 rising edge 1.96 2.04 2.07 v bor2 brown-out reset threshold 2 (bor_th[2:0]=010) falling edge 2.22 2.3 2.35 rising edge 2.31 2.41 2.44 v bor3 brown-out reset threshold 3 (bor_th[2:0]=011) falling edge 2.45 2.55 2.60 rising edge 2.54 2.66 2.7 v bor4 brown-out reset threshold 4 (bor_th[2:0]=100) falling edge 2.68 2.80 2.85 rising edge 2.78 2.90 2.95 electrical parameters stm8l15xx8, stm8l15xr6 70/129 doc id 17943 rev 5 v pvd0 pvd threshold 0 falling edge 1.80 1.84 1.88 v rising edge 1.88 1.94 1.99 v pvd1 pvd threshold 1 falling edge 1.98 2.04 2.09 rising edge 2.08 2.14 2.18 v pvd2 pvd threshold 2 falling edge 2.2 2.24 2.28 rising edge 2.28 2.34 2.38 v pvd3 pvd threshold 3 falling edge 2.39 2.44 2.48 rising edge 2.47 2.54 2.58 v pvd4 pvd threshold 4 falling edge 2.57 2.64 2.69 rising edge 2.68 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.77 2.83 2.88 rising edge 2.87 2.94 2.99 v pvd6 pvd threshold 6 falling edge 2.97 3.05 3.09 rising edge 3.08 3.15 3.20 vhyst hysteresis voltage bor0 threshold 40 mv all bor and pvd thresholds excepting bor0 100 1. data guaranteed by design, not tested in production. 2. data based on characterization results, not tested in production. table 19. embedded reset and power control block characteristics (continued) symbol parameter conditions min. typ. max. unit stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 71/129 figure 12. power supply thresholds v dd /v dda pvd o u tp u t 100 mv hy s tere s i s v pvd v bor hy s tere s i s 100 mv it en ab led bor re s et (n r s t) por/pdr re s et (nr s t) pvd bor a lw a y s a ctive por/pdr (bor not a v a il ab le) a i17211 b por v / pdr v bor/pdr re s et (nr s t) bor di sab led b y option b yte (note 1) (note 2) (note 3 ) (note 4) electrical parameters stm8l15xx8, stm8l15xr6 72/129 doc id 17943 rev 5 9.3.3 supply current characteristics total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if explicitly mentioned. in the following table, data are based on characterization results, unless otherwise specified. subject to general operating conditions for v dd and t a . table 20. total current consumption in run mode symbol para meter conditions (1) typ. max. unit 55c 85 c (2) 105 c (3) 125 c (4) i dd(run) supply current in run mode (5) all peripherals off, code executed from ram, v dd from 1.65 v to 3.6 v hsi rc osc. (16 mhz) (6) f cpu = 125 khz 0.22 0.28 0.39 0.47 0.51 ma f cpu = 1 mhz 0.32 0.38 0.49 0.57 0.61 f cpu = 4 mhz 0.59 0.65 0.76 0.84 0.88 f cpu = 8 mhz 0.93 0.99 1.1 1.18 1.22 f cpu = 16 mhz 1.62 1.68 1.79 (7) 1.87 (7) 1.91 (7) hse external clock (f cpu =f hse ) (8) f cpu = 125 khz 0.21 0.25 0.35 0.44 0.49 f cpu = 1 mhz 0.3 0.34 0.44 0.53 0.58 f cpu = 4 mhz 0.57 0.61 0.71 0.8 0.85 f cpu = 8 mhz 0.95 0.99 1.09 1.18 1.23 f cpu = 16 mhz 1.73 1.77 1.87 (7) 1.96 (7) 2.01 (7) lsi rc osc. (typ. 38 khz) f cpu = f lsi 0.029 0.035 0.039 0.044 0.055 lse external clock (32.768 khz) f cpu = f lse 0.028 0.034 0.038 0.042 0.054 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 73/129 i dd(run) supply current in run mode all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v hsi rc osc. (9) f cpu = 125 khz 0.35 0.46 0.48 0.51 0.59 ma f cpu = 1 mhz 0.54 0.65 0.67 0.7 0.78 f cpu = 4 mhz 1.16 1.27 1.29 1.32 1.4 f cpu = 8 mhz 1.97 2.08 2.1 2.13 2.21 f cpu = 16 mhz 3.54 3.65 3.67 3.7 3.78 hse external clock (f cpu =f hse ) (8) f cpu = 125 khz 0.35 0.44 0.46 0.49 0.58 f cpu = 1 mhz 0.53 0.62 0.64 0.67 0.76 f cpu = 4 mhz 1.13 1.22 1.24 1.27 1.36 f cpu = 8 mhz 2 2.09 2.11 2.14 2.23 f cpu = 16 mhz 3.69 3.78 3.8 3.83 3.92 lsi rc osc. f cpu = f lsi 0.110 0.123 0.130 0.138 0.180 lse external clock (32.768 khz) (10) f cpu = f lse 0.100 0.101 0.104 0.119 0.163 1. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc., f cpu =f sysclk 2. for devices with suffix 6 3. for devices with suffix 7 4. for devices with suffix 3 5. cpu executing typical data processing 6. the run from ram consumption can be approximated with the linear formula: i dd (run_from_ram) = freq. * 95 a/mhz + 250 a 7. tested in production. 8. oscillator bypassed (hsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the hse consumption (i dd hse ) must be added. refer to table 31 . 9. the run from flash consumption can be approximated with the linear formula: i dd (run_from_flash) = freq. * 200 a/mhz + 330 a 10. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 32 table 20. total current consumption in run mode (continued) symbol para meter conditions (1) typ. max. unit 55c 85 c (2) 105 c (3) 125 c (4) electrical parameters stm8l15xx8, stm8l15xr6 74/129 doc id 17943 rev 5 figure 13. typical i dd(run) from ram vs. v dd (hsi clock source), f cpu =16 mhz 1. typical current consumption meas ured with code executed from ram. figure 14. typical i dd(run) from flash vs. v dd (hsi clock source), f cpu = 16 mhz 1. typical current consumption meas ured with code executed from flash. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ) $ $ 2 u n ( 3 ) - ( z m ! 6 $ $ 6 25c 85c 105c 125c -40c - 3 6 1.5 2 2.5 3 3.5 4 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ) $ $ 2 u n ( 3 ) % % 0 - ( z m ! 6 $ $ 6 25c 85c 105c 125c -40c - 3 6 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 75/129 in the following table, data are based on characterization results, unless otherwise specified. table 21. total current consumption in wait mode symbol parameter conditions (1) typ max unit 55c 85 c (2) 105 c (3) 125 c (4) i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from ram with flash in i ddq mode, (5) v dd from 1.65 v to 3.6 v hsi f cpu = 125 khz 0.21 0.29 0.33 0.36 0.43 ma f cpu = 1 mhz 0.25 0.33 0.37 0.4 0.47 f cpu = 4 mhz 0.32 0.4 0.44 0.47 0.54 f cpu = 8 mhz 0.42 0.496 0.54 0.56 0.64 f cpu = 16 mhz 0.66 0.736 0.78 (6) 0.8 (6) 0.88 (6) hse external clock (f cpu =f hse ) (7) f cpu = 125 khz 0.19 0.21 0.3 0.35 0.41 f cpu = 1 mhz 0.2 0.23 0.32 0.36 0.43 f cpu = 4 mhz 0.27 0.3 0.39 0.43 0.5 f cpu = 8 mhz 0.37 0.4 0.49 0.53 0.6 f cpu = 16 mhz 0.63 0.66 0.75 (6) 0.79 (6) 0.86 (6) lsi f cpu = f lsi 0.028 0.037 0.039 0.044 0.054 lse (8) external clock (32.768 khz) f cpu = f lse 0.027 0.035 0.038 0.042 0.051 electrical parameters stm8l15xx8, stm8l15xr6 76/129 doc id 17943 rev 5 i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v hsi f cpu = 125 khz 0.27 0.36 0.42 0.46 0.51 ma f cpu = 1 mhz 0.29 0.38 0.44 0.48 0.53 f cpu = 4 mhz 0.37 0.46 0.52 0.56 0.61 f cpu = 8 mhz 0.45 0.55 0.61 0.65 0.7 f cpu = 16 mhz 0.69 0.79 0.85 0.89 0.94 hse (7) external clock (f cpu = hse) f cpu = 125 khz 0.23 0.29 0.32 0.4 0.47 f cpu = 1 mhz 0.24 0.31 0.34 0.41 0.48 f cpu = 4 mhz 0.32 0.39 0.42 0.49 0.56 f cpu = 8 mhz 0.42 0.49 0.51 0.59 0.66 f cpu = 16 mhz 0.7 0.77 0.79 0.87 0.94 lsi f cpu = f lsi 0.037 0.085 0.105 0.123 0.153 lse (8) external clock (32.768 khz) f cpu = f lse 0.036 0.082 0.095 0.119 0.133 1. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc., f cpu = f sysclk 2. for devices with suffix 6. 3. for devices with suffix 7. 4. for devices with suffix 3. 5. flash is configured in i ddq mode in wait mode by setting the epm or waitm bit in the flash_cr1 register. 6. tested in production. 7. oscillator bypassed (hsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the hse consumption (i dd hse ) must be added. refer to table 31 . 8. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd hse ) must be added. refer to table 32 table 21. total current consumption in wait mode (continued) symbol parameter conditions (1) typ max unit 55c 85 c (2) 105 c (3) 125 c (4) stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 77/129 figure 15. typical i dd(wait) from ram vs. v dd (hsi clock source), f cpu = 16 mhz 1. typical current consumption meas ured with code executed from ram. figure 16. typical i dd(wait) from flash (hsi clock source), f cpu = 16 mhz 1. typical current consumption meas ured with code executed from flash. 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 idd wait hsi 16mhz (m a) v dd (v) 25c 85c - 40c ms19113v1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 idd wfi hsi 16mhz eeon (ma) v dd (v) 25c 85c 105c 125c -40c - 3 6 electrical parameters stm8l15xx8, stm8l15xr6 78/129 doc id 17943 rev 5 in the following table, data are based on characterization results, unless otherwise specified. table 22. total current consumption and timing in low power run mode at v dd = 1.65 v to 3.6 v symbol parameter conditions (1) typ. max. unit i dd(lpr) supply current in low power run mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 5.86 6.38 a t a = 55 c 6.52 7.06 t a = 85 c 7.68 8.7 t a = 105 c 10.14 11.77 t a = 125 c 14.4 18.27 with tim2 active (2) t a = -40 c to 25 c 6.2 6.73 t a = 55 c 6.86 7.41 t a = 85 c 9.71 10.81 t a = 105 c 13.17 15.39 t a = 125 c 16.72 21.1 lse (3) external clock (32.768 khz) all peripherals off t a = -40 c to 25 c 5.42 5.94 t a = 55 c 5.9 6.52 t a = 85 c 6.14 6.8 t a = 105 c 7.46 8.2 t a = 125 c 10.25 12.81 with tim2 active (2) t a = -40 c to 25 c 5.87 6.48 t a = 55 c 6.44 6.95 t a = 85 c 6.7 7.65 t a = 105 c 8.01 9.15 t a = 125 c 10.62 16.09 1. no floating i/os 2. timer 2 clock enabl ed and counter running 3. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 32 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 79/129 figure 17. typical i dd(lpr) vs. v dd (lsi clock source), all peripherals off 0 0.005 0.01 0.015 0.02 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 idd lp run lsi all off (ma) v dd (v) 25c 85c ms19110v1 electrical parameters stm8l15xx8, stm8l15xr6 80/129 doc id 17943 rev 5 in the following table, data are based on characterization results, unless otherwise specified. table 23. total current consumption in low power wait mode at v dd = 1.65 v to 3.6 v symbol parameter conditions (1) typ. max. unit i dd(lpw) supply current in low power wait mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 3.03 3.41 a t a = 55 c 3.38 3.78 t a = 85 c 4.6 5.34 t a = 105 c 7.25 8.84 t a = 125 c 11.89 16.18 with tim2 active (2) t a = -40 c to 25 c 3.78 4.21 t a = 55 c 4.13 4.57 t a = 85 c 5.29 6.08 t a = 105 c 7.54 9.13 t a = 125 c 12.47 15.56 lse external clock (3) (32.768 khz) all peripherals off t a = -40 c to 25 c 2.46 2.89 t a = 55 c 2.58 3.07 t a = 85 c 3.32 4.05 t a = 105 c 4.63 6.17 t a = 125 c 7.52 11.68 with tim2 active (2) t a = -40 c to 25 c 2.88 3.29 t a = 55 c 2.97 3.42 t a = 85 c 3.69 4.55 t a = 105 c 5.09 6.78 t a = 125 c 7.91 12.15 1. no floating i/os. 2. timer 2 clock enabled and counter is running. 3. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 32 . stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 81/129 figure 18. typical i dd(lpw) vs. v dd (lsi clock source), all peripherals off 1. typical current consumption meas ured with code executed from ram. 0 0.005 0.01 0.015 0.02 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ) $ $ , p 7 f i r a m , 3 ) a l l o f f m ! 6 $ $ 6 25c 85c 105c 125c -40c . 4 7 electrical parameters stm8l15xx8, stm8l15xr6 82/129 doc id 17943 rev 5 in the following table, data are based on characterization results, unless otherwise specified. table 24. total current consumption and timing in active-halt mode at v dd = 1.65 v to 3.6 v symbol parameter conditions (1) typ. max. unit i dd(ah) supply current in active-halt mode lsi rc (at 38 khz) lcd off (2) t a = -40 c to 25 c 0.92 2.25 a t a = 55 c 1.32 3.44 t a = 85 c 1.63 3.87 t a = 105 c 3 7.94 t a = 125 c 5.6 13.8 lcd on (static duty/ external v lcd ) (3) t a = -40 c to 25 c 1.56 3.6 t a = 55 c 1.64 3.8 t a = 85 c 2.12 5.03 t a = 105 c 3.34 8.2 t a = 125 c 5.83 14.4 lcd on (1/4 duty/ external v lcd ) (4) t a = -40 c to 25 c 1.92 4.56 t a = 55 c 2.1 4.97 t a = 85 c 2.6 6.14 t a = 105 c 3.62 8.49 t a = 125 c 6.1 15.92 lcd on (1/4 duty/ internal v lcd ) (5) t a = -40 c to 25 c 4.2 9.88 t a = 55 c 4.39 10.32 t a = 85 c 4.84 11.5 t a = 105 c 5.98 15 t a = 125 c 7.21 18.07 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 83/129 i dd(ah) supply current in active-halt mode lse external clock (32.768 khz) (6) lcd off (7) t a = -40 c to 25 c 0.54 1.35 a t a = 55 c 0.61 1.44 t a = 85 c 0.91 2.27 t a = 105 c 2.24 5.42 t a = 125 c 5.03 12 lcd on (static duty/ external v lcd ) (3) t a = -40 c to 25 c 0.91 2.13 t a = 55 c 1.05 2.55 t a = 85 c 1.42 3.65 t a = 105 c 2.63 6.35 t a = 125 c 5.24 13.15 lcd on (1/4 duty/ external v lcd ) (4) t a = -40 c to 25 c 1.6 2.84 t a = 55 c 1.76 4.37 t a = 85 c 2.14 5.23 t a = 105 c 3.37 8.5 t a = 125 c 5.92 15.19 lcd on (1/4 duty/ internal v lcd ) (5) t a = -40 c to 25 c 3.89 9.15 t a = 55 c 3.89 9.15 t a = 85 c 4.25 10.49 t a = 105 c 5.42 16.31 t a = 125 c 6.58 16.6 i dd(wufah) supply current during wakeup time from active-halt mode (using hsi) 2.4 ma t wu_hsi(ah) (8)(9) wakeup time from active-halt mode to run mode (using hsi) 4.7 7 s t wu_lsi(ah) (8)(9) wakeup time from active-halt mode to run mode (using lsi) 150 s 1. no floating i/o, unles s otherwise specified. 2. rtc enabled. clock source = lsi 3. rtc enabled, lcd enabled with external v lcd = 3 v, static duty, division ratio = 256, all pixels active, no lcd connected. 4. rtc enabled, lcd enabled with external v lcd , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no lcd connected. 5. lcd enabled with internal lcd booster v lcd = 3 v, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no lcd connected. 6. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 32 table 24. total current consumption and timing in active-halt mode at v dd = 1.65 v to 3.6 v (continued) symbol parameter conditions (1) typ. max. unit electrical parameters stm8l15xx8, stm8l15xr6 84/129 doc id 17943 rev 5 figure 19. typical i dd(ah) vs. v dd (lsi clock source) 7. rtc enabled. clock source = lse 8. wakeup time until start of interrupt vector fetch. the first word of interrupt routi ne is fetched 4 cpu cycles after t wu . 9. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register. table 25. typical current consumption in active-halt mode, rtc clocked by lse external crystal symbol parameter condition (1) typ. unit i dd(ah) (2) supply current in active-halt mode v dd = 1.8 v lse 1.2 a lse/32 (3) 0.9 v dd = 3 v lse 1.4 lse/32 (3) 1.1 v dd = 3.6 v lse 1.6 lse/32 (3) 1.3 1. no floating i/o, unles s otherwise specified. 2. based on measurements on bench with 32. 768 khz external cr ystal oscillator. 3. rtc clock is lse divided by 32. 0 0.005 0.01 0.015 0.02 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ) $ $ ! ( a l t m ! 6 $ $ 6 25c 85c 105c 125c -40c - 3 6 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 85/129 in the following table, data are based on characterization results, unless otherwise specified. figure 20. typical i dd(halt) vs. v dd (internal reference voltage off) table 26. total current consumption and timing in halt mode at v dd = 1.65 to 3.6 v symbol parameter condition (1) typ. max. unit i dd(halt) supply current in halt mode (ultra low power ulp bit =1 in the pwr_csr2 register) t a = -40 c to 25 c 400 1600 (2) na t a = 55 c 810 2400 t a = 85 c 1600 4500 (2) t a = 105 c 2900 7700 (2) t a = 125 c 5.6 18 (2) a i dd(wuhalt) supply current during wakeup time from halt mode (using hsi) 2.4 ma t wu_hsi(halt) (3)(4) wakeup time from halt to run mode (using hsi) 4.7 7 s t wu_lsi(halt) (3)(4) wakeup time from halt mode to run mode (using lsi) 150 s 1. t a = -40 to 125 c, no floating i/o, unless otherwise specified 2. tested in production 3. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register 4. wakeup time until start of interrupt vector fetch. the first word of interrupt routi ne is fetched 4 cpu cycles after t wu 0006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 ) $ $ ( a l t b g o f f m ! 25c 85c 105c 125c -40c 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 ) $ $ ( a l t b g o f f m ! 6 $ $ 6 25c 85c 105c 125c -40c - 3 6 electrical parameters stm8l15xx8, stm8l15xr6 86/129 doc id 17943 rev 5 current consumption of on-chip peripherals table 27. peripheral current consumption symbol parameter typ. v dd = 3.0 v unit i dd(tim1) tim1 supply current (1) 10 a/mhz i dd(tim2) tim2 supply current (1) 7 i dd(tim3) tim3 supply current (1) 7 i dd(tim5) tim5 supply current (1) 7 i dd(tim4) tim4 timer supply current (1) 3 i dd(usart1) usart1 supply current (2) 5 i dd(usart2) usart2 supply current (2) 5 i dd(usart3) usart3 supply current (2) 5 i dd(spi1) spi1 supply current (2) 3 i dd(spi2) spi2 supply current (2) 3 i dd(i2c1) i 2 c1 supply current (2) 4 i dd(dma1) dma1 supply current (2) 3 i dd(wwdg) wwdg supply current (2) 1 i dd(all) peripherals on (3) 63 i dd(adc1) adc1 supply current (4) 1500 a i dd(dac) dac supply current (5) 370 i dd(comp1) comparator 1 supply current (6) 0.160 i dd(comp2) comparator 2 supply current (6) slow mode 2 fast mode 5 i dd(pvd/bor) power voltage detector and brownout reset unit supply current (7) 2.6 i dd(bor) brownout reset unit supply current (7) 2.4 i dd(idwdg) independent watchdog supply current including lsi supply current 0.45 excluding lsi supply current 0.05 1. data based on a differential i dd measurement between all peripherals off an d a timer counter running at 16 mhz. the cpu is in wait mode in both cases. no ic/oc progr ammed, no i/o pins toggling. not tested in production. 2. data based on a differential i dd measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. the cpu is in wait mode in both cases. no i/o pins toggling. not tested in production. 3. peripherals listed above the i dd(all) parameter on: tim1, tim2, tim3, tim4, tim5, usart1, usart2, usart3, spi1, spi2, i2c1, dma1, wwdg. 4. data based on a differential i dd measurement between adc in reset conf iguration and contin uous adc conversion. stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 87/129 9.3.4 clock and timi ng characteristics hse external clock (hsebyp = 1 in clk_eckcr) subject to general operating conditions for v dd and t a . 5. data based on a differential i dd measurement between dac in reset conf iguration and continuous dac conversion of v dd /2. floating dac output. 6. data based on a differential i dd measurement between comp1 or comp2 in reset configuration and comp1 or comp2 enabled with static inputs. supply current of internal reference voltage excluded. 7. including supply current of internal reference voltage. table 28. current consumption under external reset symbol parameter conditions typ. unit i dd(rst) supply current under external reset (1) pb1/pb3/pa5 pins are externally tied to v dd v dd = 1.8 v 48 a v dd = 3 v 80 v dd = 3.6 v 95 1. all pins except pa0, pb0 and pb4 are floating under rese t. pa0, pb0 and pb4 are confi gured with pull-up under reset. pb1, pb3 and pa5 must be tied externally under reset to avoid the consumption due to their schmitt trigger. table 29. hse external clock characteristics symbol parameter conditions min. typ. max. unit f hse_ext (1) 1. guaranteed by design, not tested in production. external clock source frequency 116mhz v hseh osc_in input pin high level voltage 0.7 x v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3 x v dd c in(hse) (1) osc_in input capacitance 2.6 pf i leak_hse osc_in input leakage current v ss < v in < v dd 1 a electrical parameters stm8l15xx8, stm8l15xr6 88/129 doc id 17943 rev 5 lse external clock (lsebyp=1 in clk_eckcr) the lse is available on stm8l151xx and stm8l152xx devices only. subject to general operating conditions for v dd and t a . hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mhz crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). table 30. lse external clock characteristics symbol parameter min. typ. max. unit f lse_ext (1) external clock source frequency 32.768 khz v lseh (2) osc32_in input pin high level voltage 0.7 x v dd v dd v v lsel (2) osc32_in input pin low level voltage v ss 0.3 x v dd c in(lse) (1) osc32_in input capacitance 0.6 pf i leak_lse osc32_in input leakage current 1 a 1. guaranteed by design, not tested in production. 2. data based on characterization results, not tested in production. table 31. hse oscillator characteristics symbol parameter conditions min. typ. max. unit f hse high speed external oscillator frequency 116mhz r f feedback resistor 200 k c (1)(2) recommended load capacitance 20 pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz 2.5 (startup) 0.7 (stabilized) (3) ma c = 10 pf, f osc =16 mhz 2.5 (startup) 0.46 (stabilized) (3) g m oscillator transconductance 3.5 (3) ma/v t su(hse) (4) startup time v dd is stabilized 1 ms 1. c= c l1 = c l2 is approximately equiva lent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. guaranteed by design. not tested in production. 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabili zed 16 mhz oscillation. this value is measured for a standar d crystal resonator and it can vary signi ficantly with the crystal manufacturer. stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 89/129 figure 21. hse oscillator circuit diagram hse oscillator critical g m formula r m : motional resistance (see crystal specification), l m : motional inductance (see crystal specification), c m : motional capacitance (see crystal specification), co: shunt capacitance (see crystal specification), c l1 =c l2 =c: grounded external capacitance g m >> g mcrit lse crystal/ceramic resonator oscillator the lse is available on stm8l151xx and stm8l152xx devices only. the lse clock can be supplied with a 32.768 kh z crystal/ceramic resonator oscillator. all the information given in this paragraph is based on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscilla tor pins in order to minimize output distortion and startup stabilization time. refer to the crys tal resonator manufactur er for more details (frequency, package, accuracy...). osc_out osc_in f hse to core c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator g mcrit 2 f hse () 2 r m 2co c + () 2 = table 32. lse oscillator characteristics symbol parameter conditions min. typ. max. unit f lse low speed external oscillator frequency 32.768 khz r f feedback resistor v = 200 mv 1.2 m c (1)(2) recommended load capacitance 8 pf i dd(lse) lse oscillator power consumption v dd = 1.8 v 450 na v dd = 3 v 600 v dd = 3.6 v 750 g m oscillator transconductance 3 (3) a/v t su(lse) (4) startup time v dd is stabilized 1 s 1. c= c l1 = c l2 is approximately equiva lent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of s upply current using a high qualit y resonator with a small r m value. refer to crystal manufacturer for more details. 3. guaranteed by design. not tested in production. 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabi lized 32.768 khz oscillation. this value is measured for a standard crys tal resonator and it can vary signific antly with the crystal manufacturer. electrical parameters stm8l15xx8, stm8l15xr6 90/129 doc id 17943 rev 5 figure 22. lse oscillator circuit diagram internal clock sources subject to general operating conditions for v dd , and t a . high speed internal rc oscillator (hsi) in the following table, data are based on characterization results, not tested in production, unless otherwise specified. osc_out osc_in f lse c l1 c l2 r f stm8 resonator consumption control g m r m c m l m c o resonator table 33. hsi oscillator characteristics symbol parameter conditions (1) min. typ. max. unit f hsi frequency v dd = 3.0 v 16 mhz acc hsi accuracy of hsi oscillator (factory calibrated) v dd = 3.0 v, t a = 25 c -1 (2) 1 (2) % v dd = 3.0 v, 0 c t a 55 c -1.5 1.5 % v dd = 3.0 v, -10 c t a 70 c -2 2 % v dd = 3.0 v, -10 c t a 85 c -2.5 2 % v dd = 3.0 v, -10 c t a 125 c -4.5 2 % 1.65 v v dd 3.6 v, -40 c t a 125 c -4.5 3 % trim hsi user trimming step (3) trimming code multiple of 16 0.4 0.7 % trimming code = multiple of 16 1.5 % t su(hsi) hsi oscillator setup time (wakeup time) 3.7 6 (4) s i dd(hsi) hsi oscillator power consumption 100 140 (4) a 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. 2. tested in production. 3. the trimming step differs depending on t he trimming code. it is usua lly negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). refer to the an3101 ?stm8l15x internal rc oscillator calib ration? application note for more details. 4. guaranteed by design, not tested in production stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 91/129 figure 23. typical hsi frequency vs. v dd low speed internal rc oscillator (lsi) in the following table, data are based on characterization results, not tested in production. table 34. lsi oscillator characteristics symbol parameter conditions (1) 1. v dd = 1.65 v to 3.6 v, t a = -40 to 125 c unless otherwise specified. min. typ. max. unit f lsi frequency 26 38 56 khz t su(lsi) lsi oscillator wakeup time 200 (2) 2. guaranteed by design, not tested in production. s d (lsi) lsi oscillator frequency drift (3) 3. this is a deviation for an individual part, once the in itial frequency has been measured. 0 c t a 85 c -12 11 % 6 $ $ ; 6 = ( 3 ) f r e q u e n c y ; - ( z = ? # ? # ? # ? # a i electrical parameters stm8l15xx8, stm8l15xr6 92/129 doc id 17943 rev 5 figure 24. typical lsi clock source frequency vs. v dd 9.3.5 memory characteristics t a = -40 to 125 c unless otherwise specified. 0.03 0.032 0.034 0.036 0.038 0.04 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 2 # + # h e c k - ( z 6 $ $ 6 25c 85c 105c 125c -40c - 3 6 table 35. ram and hardware registers symbol parameter conditions min. typ. max. unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by characterization, not tested in production. halt mode (or reset) 1.65 v stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 93/129 flash memory table 36. flash program and data eeprom memory symbol parameter conditions min. typ. max. (1) unit v dd operating voltage (all modes, read/write/erase) f sysclk = 16 mhz 1.65 3.6 v t prog programming time for 1 or 128 bytes (block) erase/write cycles (on programmed byte) 6ms programming time for 1 to 128 bytes (block) write cycles (on erased byte) 3ms i prog programming/ erasing consumption t a = +25 c, v dd = 3.0 v 0.7 ma t a = +25 c, v dd = 1.8 v t ret (2) data retention (program memory) after 10000 erase/write cycles at t a =? 40 +85 c (6 suffix) t ret = +85 c 30 (1) years data retention (program memory) after 10000 erase/write cycles at t a =? 40 +125 c (3 suffix) t ret = +125 c 5 (1) data retention (data memory) after 300000 erase/write cycles at t a =? 40 +85 c (6 suffix) t ret = +85 c 30 (1) data retention (data memory) after 300000 erase/write cycles at t a =? 40 +125 c (3 suffix) t ret = +125 c 5 (1) n rw (3) erase/write cycles (program memory) t a =? 40 +85 c (6 suffix), t a =? 40 +105 c (7 suffix) or t a =? 40 +125 c (3 suffix) 10 (1) kcycles erase/write cycles (data memory) 300 (1) (4) 1. data based on characterization results, not tested in production. 2. conforming to jedec jesd22a117 3. the physical granularity of the memory is 4 bytes, so cycl ing is performed on 4 bytes even when a write/erase operation addresses a single byte. 4. data based on characterization performed on the whole data memory. electrical parameters stm8l15xx8, stm8l15xr6 94/129 doc id 17943 rev 5 9.3.6 i/o current inj ection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susc eptibility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode. while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, lcd levels, etc.). the test results are give n in the following table. 9.3.7 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 37. i/o current injection susceptibility symbol description functional su sceptibility unit negative injection positive injection i inj injected current on true open-drain pins -5 +0 ma injected current on all 5 v tolerant (ft) pins -5 +0 injected current on any other pin -5 +5 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 95/129 table 38. i/o static characteristics symbol parameter conditions (1) min. typ. max. unit v il input low level voltage (2) input voltage on true open-drain pins (pc0 and pc1) vss-0.3 0.3 x v dd v input voltage on five- volt tolerant (ft) pins vss-0.3 0.3 x v dd input voltage on any other pin vss-0.3 0.3 x v dd v ih input high level voltage (2) input voltage on true open-drain pins (pc0 and pc1) with v dd < 2 v 0.70 x v dd 5.2 v input voltage on true open-drain pins (pc0 and pc1) with v dd 2 v 5.5 input voltage on five- volt tolerant (ft) pins with v dd < 2 v 0.70 x v dd 5.2 input voltage on five- volt tolerant (ft) pins with v dd 2 v 5.5 input voltage on any other pin 0.70 x v dd v dd +0.3 v hys schmitt trigger voltage hysteresis (3) standard i/os 200 mv true open drain i/os 200 i lkg input leakage current (4) v ss v in v dd standard i/os --50 (5) na v ss v in v dd true open drain i/os - - 200 (5) v ss v in v dd pa0 with high sink led driver capability - - 200 (5) r pu weak pull-up equivalent resistor (2)(6) v in = v ss 30 45 60 k c io i/o pin capacitance 5 pf 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. 2. data based on characterization results, not tested in production. 3. hysteresis voltage between schmitt trigger switchin g levels. based on characterization results, not tested. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. not tested in production. 6. r pu pull-up equivalent resistor based on a resistive transistor (corresponding i pu current characteristics described in figure 28 ). electrical parameters stm8l15xx8, stm8l15xr6 96/129 doc id 17943 rev 5 figure 25. typical v il and v ih vs. v dd (standard i/os) figure 26. typical v il and v ih vs. v dd (true open drain i/os) figure 27. typical pull-up resistance r pu vs. v dd with v in =v ss 6 $ $ ; 6 = 6 ) , a n d 6 ) ( ; 6 = ? # ? # ? # ? # a i 6 $ $ ; 6 = 6 ) , a n d 6 ) ( ; 6 = ? # ? # ? # ? # a i 6 $ $ ; 6 = 0 u l l 5 p r e s i s t a n c e ; k 7 = ? # ? # ? # ? # a i stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 97/129 figure 28. typical pull-up current i pu vs. v dd with v in =v ss output driving current subject to general operating conditions for v dd and t a unless otherwise specified. table 39. output driving current (high sink ports) i/o type symbol parameter conditions min. max. unit standard v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 16 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +2 ma, v dd = 3.0 v 0.45 v i io = +2 ma, v dd = 1.8 v 0.45 v i io = +10 ma, v dd = 3.0 v 0.7 v v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in table 16 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin i io = -2 ma, v dd = 3.0 v v dd -0.45 v i io = -1 ma, v dd = 1.8 v v dd -0.45 v i io = -10 ma, v dd = 3.0 v v dd -0.7 v 6 $ $ ; 6 = 0 u l l 5 p c u r r e n t ; ? ! = ? # ? # ? # ? # a i electrical parameters stm8l15xx8, stm8l15xr6 98/129 doc id 17943 rev 5 table 40. output driving current (true open drain ports) i/o type symbol parameter conditions min. max. unit open drain v ol (1) output low level voltage for an i/o pin i io = +3 ma, v dd = 3.0 v 0.45 v i io = +1 ma, v dd = 1.8 v 0.45 1. the i io current sunk must always respect the absolute maximum rating specified in table 16 and the sum of i io (i/o ports and control pins) must not exceed i vss . table 41. output driving current (pa0 wi th high sink led driver capability) i/o type symbol parameter conditions min. max. unit ir v ol (1) output low level voltage for an i/o pin i io = +20 ma, v dd = 2.0 v 0.45 v 1. the i io current sunk must always respect the absolute maximum rating specified in table 16 and the sum of i io (i/o ports and control pins) must not exceed i vss . figure 29. typical v ol @ v dd = 3.0 v (high sink ports) figure 30. typical v ol @ v dd = 1.8 v (high sink ports) ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # a i ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # a i figure 31. typical v ol @ v dd = 3.0 v (true open drain ports) figure 32. typical v ol @ v dd = 1.8 v (true open drain ports) a i ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # b j stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 99/129 nrst pin subject to general operating conditions for v dd and t a unless otherwise specified. figure 33. typical v dd - v oh @ v dd = 3.0 v (high sink ports) figure 34. typical v dd - v oh @ v dd = 1.8 v (high sink ports) ) / ( ; m ! = 6 $ $ 6 / ( ; 6 = ? # ? # ? # ? # a i ) / ( ; m ! = 6 $ $ 6 / ( ; 6 = ? # ? # ? # ? # b j table 42. nrst pin characteristics symbol parameter conditions min. typ. max. unit v il(nrst) nrst input low level voltage (1) v ss 0.8 v v ih(nrst) nrst input high level voltage (1) 1.4 v dd v ol(nrst) nrst output low level voltage (1) i ol = 2 ma for 2.7 v v dd 3.6 v 0.4 i ol = 1.5 ma for v dd < 2.7 v v hyst nrst input hysteresis (3) 10%v dd (2) mv r pu(nrst) nrst pull-up equivalent resistor (1) 30 45 60 k v f(nrst) nrst input filtered pulse (3) 50 ns v nf(nrst) nrst input not filtered pulse (3) 300 1. data based on characterization results, not tested in production. 2. 200 mv min. 3. data guaranteed by design, not tested in production. electrical parameters stm8l15xx8, stm8l15xr6 100/129 doc id 17943 rev 5 figure 35. typical nrst pull-up resistance r pu vs. v dd figure 36. typical nrst pull-up current i pu vs. v dd the reset network shown in figure 37 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il max. level specified in ta bl e 4 2 . otherwise the reset is not taken into account internally. for power consumption- sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. if the nrst signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. the minimum recommended capacity is 10 nf. figure 37. recommended nrst pin configuration 6 $ $ ; 6 = 0 u l l u p r e s i s t a n c e ; k 7 = ? # ? # ? # ? # a i a i 6 $ $ ; 6 = 0 u l l 5 p c u r r e n t ; ? ! = ? # ? # ? # ? # 0.1 f external reset circuit stm8l filter r pu v dd internal reset rstin stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 101/129 9.3.8 communication interfaces spi1 - serial peripheral interface unless otherwise specified, the parameters given in ta bl e 4 3 are derived from tests performed under ambient temperature, f sysclk frequency and v dd supply voltage conditions summarized in section 9.3.1 . refer to i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso). table 43. spi1 characteristics symbol parameter conditions (1) min. max. unit f sck 1/t c(sck) spi1 clock frequency master mode 0 8 mhz slave mode 0 8 t r(sck) t f(sck) spi1 clock rise and fall time capacitive load: c = 30 pf - 30 ns t su(nss) (2) nss setup time slave mode 4 x 1/f sysclk - t h(nss) (2) nss hold time slave mode 80 - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f master = 8 mhz, f sck = 4 mhz 105 145 t su(mi) (2) t su(si) (2) data input setup time master mode 30 - slave mode 3 - t h(mi) (2) t h(si) (2) data input hold time master mode 15 - slave mode 0 - t a(so) (2)(3) data output access time slave mode - 3x 1/f sysclk t dis(so) (2)(4) data output disable time slave mode 30 - t v(so) (2) data output valid time slave mode (after enable edge) - 60 t v(mo) (2) data output valid time master mode (after enable edge) -20 t h(so) (2) data output hold time slave mode (after enable edge) 15 - t h(mo) (2) master mode (after enable edge) 1- 1. parameters are given by se lecting 10 mhz i/o output frequency. 2. values based on design simulation and/or charac terization results, and not tested in production. 3. min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data. 4. min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in hi-z. electrical parameters stm8l15xx8, stm8l15xr6 102/129 doc id 17943 rev 5 figure 38. spi1 timing diagram - slave mode and cpha=0 figure 39. spi1 timing diagram - slave mode and cpha=1 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134 sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 103/129 figure 40. spi1 timing diagram - master mode 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / electrical parameters stm8l15xx8, stm8l15xr6 104/129 doc id 17943 rev 5 i 2 c - inter ic control interface subject to general operating conditions for v dd , f sysclk , and t a unless otherwise specified. the stm8l i 2 c interface (i2c1) meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: refer to i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl). note: for speeds around 200 khz, the achieved speed can have a 5% tolerance. for other speed ranges, the achieved speed can have a 2% tolerance. the above variations depend on the accuracy of the external components used. table 44. i2c characteristics symbol parameter standard mode i 2 cfast mode i 2 c (1) 1. f sysclk must be at least equal to 8 mhz to achieve max fast i 2 c speed (400 khz). unit min. (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max. (2) min. (2) max. (2) t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 0 900 t r(sda) t r(scl) sda and scl rise time 1000 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 s c b capacitive load for each bus line 400 400 pf stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 105/129 figure 41. typical application with i 2 c bus and timing diagram 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd repeated start start stop start t f(sda) t r(sda) t su(sda) t h(sda) t f(scl) t r(scl) t w(scll) t w(sclh) t h(sta) t su(sto) t su(sta) t w(sto:sta) sda scl 4.7k sda stm8l scl v dd 100 100 v dd 4.7k i 2 cbus electrical parameters stm8l15xx8, stm8l15xr6 106/129 doc id 17943 rev 5 9.3.9 lcd control ler (stm8l152xx only) in the following table, data are guaranteed by design, not tested in production. vlcd external capacitor (stm8l152xx only) the application can achieve a stabilized lcd reference voltage by connecting an external capacitor c ext to the v lcd pin. c ext is specified in ta bl e 4 5 . table 45. lcd characteristics symbol parameter min. typ. max. unit v lcd lcd external voltage 3.6 v v lcd0 lcd internal reference voltage 0 2.6 v lcd1 lcd internal reference voltage 1 2.7 v lcd2 lcd internal reference voltage 2 2.8 v lcd3 lcd internal reference voltage 3 3.0 v lcd4 lcd internal reference voltage 4 3.1 v lcd5 lcd internal reference voltage 5 3.2 v lcd6 lcd internal reference voltage 6 3.4 v lcd7 lcd internal reference voltage 7 3.5 c ext v lcd external capacitance 0.1 1 2 f i dd supply current (1) at v dd = 1.8 v 1. lcd enabled with 3 v internal booster (lcd_cr1 = 0x08), 1/ 4 duty, 1/3 bias, division ratio= 64, all pixels active, no lcd connected. 3 a supply current (1) at v dd = 3 v 3 r hn (2) 2. r hn is the total high value resistive network. high value resistive network (low drive) 6.6 m r ln (3) 3. r ln is the total low value resistive network. low value resistive network (high drive) 240 k v 33 segment/common higher level voltage v lcdx v v 34 segment/common 3/4 level voltage 3/4v lcdx v 23 segment/common 2/3 level voltage 2/3v lcdx v 12 segment/common 1/2 level voltage 1/2v lcdx v 13 segment/common 1/3 level voltage 1/3v lcdx v 14 segment/common 1/4 level voltage 1/4v lcdx v 0 segment/common lowest level voltage 0 stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 107/129 9.3.10 embedded reference voltage in the following table, data are based on characterization results, not tested in production, unless otherwise specified. table 46. reference voltage characteristics symbol parameter conditions min. typ. max. unit i refint internal reference voltage consumption 1.4 a t s_vrefint (1)(2) adc sampling time when reading the internal reference voltage 510 s i buf (1) internal reference voltage buffer consumption (used for adc) 13.5 25 a v refint out reference voltage output 1.202 (3) 1.224 1.242 (3) v i lpbuf (1) internal reference voltage low power buffer consumption (used for comparators or output) 730 1200 na i refout (1)(4) buffer output current 1 a c refout reference voltage output load 50 pf t vrefint (1) internal reference voltage startup time 23 ms t bufen (1)(2) internal reference voltage buffer startup time once enabled 10 s acc vrefint (5) accuracy of v refint stored in the vrefint_factory_conv byte 5 mv stab vrefint stability of v refint over temperature -40 c t a 125 c 20 50 ppm/c stability of v refint over temperature 0 c t a 50 c 20 ppm/c stab vrefint stability of v refint after 1000 hours 1000 ppm 1. guaranteed by design, not tested in production 2. defined when adc output reaches its final value 1/2lsb 3. tested in production at v dd = 3 v 10 mv. 4. to guarantee less than 1% v refout deviation 5. measured at v dd = 3 v 10 mv. this value takes into account v dd accuracy and adc conversion accuracy. electrical parameters stm8l15xx8, stm8l15xr6 108/129 doc id 17943 rev 5 9.3.11 temperature sensor in the following table, data are based on characterization results, not tested in production, unless otherwise specified. 9.3.12 comparator characteristics in the following tables, data are guaranteed by design, not tested in production. table 47. ts characteristics symbol parameter min. typ. max. unit v 90 (1) 1. tested in production at v dd = 3 v 10 mv. the 8 lsb of the v 90 adc conversion result are stored in the ts_factory_conv_v90 byte. sensor reference voltage at 90c 5 c, 0.580 0.597 0.614 v t l v sensor linearity with temperature 1 2 c avg_slope (2) average slope 1.59 1.62 1.65 mv/c idd (temp) (2) consumption 3.4 6 a t start (2)(3) 2. guaranteed by design, not tested in production. 3. defined for adc output reaching its final value 1/2lsb. temperature sensor startup time 10 s t s_temp (2) adc sampling time when reading the temperature sensor 510s table 48. comparator 1 characteristics symbol parameter conditions min (1) typ max (1) 1. based on characterization , not tested in production. unit v dda analog supply voltage 1.65 3.6 v r 400k r 400k value 400 k r 10k r 10k value 10 v in comparator 1 input voltage range 0.6 v dda v t start comparator startup time 7 10 s td propagation delay (2) 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 310 voffset comparator offset 3 10 mv d voffset /dt comparator offset variation in worst voltage stress conditions v dda = 3.6 v v in+ = 0 v v in- = v refint t a = 25 c 0 1.5 10 mv/1000 h i comp1 current consumption (3) 3. comparator consumption only. inte rnal reference voltage not included. 160 260 na stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 109/129 table 49. comparator 2 characteristics symbol parameter conditions min typ max (1) unit v dda analog supply voltage 1.65 3.6 v v in comparator 2 input voltage range 0 v dda v t start comparator startup time fast mode 15 20 s slow mode 20 25 t d slow propagation delay (2) in slow mode 1.65 v v dda 2.7 v 1.8 3.5 2.7 v v dda 3.6 v 2.5 6 t d fast propagation delay (2) in fast mode 1.65 v v dda 2.7 v 0.8 2 2.7 v v dda 3.6 v 1.2 4 v offset comparator offset error 4 20 mv dthreshold/ dt threshold voltage temperature coefficient v dda = 3.3v t a = 0 to 50 c v- = v ref+ , 3/4 v ref+ , 1/2 v ref+ , 1/4 v ref+ . 15 30 ppm /c i comp2 current consumption (3) fast mode 3.5 5 a slow mode 0.5 2 1. based on characterization , not tested in production. 2. the delay is characterized for 100 mv input step wi th 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 3. comparator consumption only. inte rnal reference voltage (necessary for comparator operation) is not included. electrical parameters stm8l15xx8, stm8l15xr6 110/129 doc id 17943 rev 5 9.3.13 12-bit dac characteristics in the following table, data are guaranteed by design, not tested in production. table 50. dac characteristics symbol parameter conditions min. typ. max. unit v dda analog supply voltage 1.8 3.6 v v ref+ reference supply voltage 1.8 v dda i vref current consumption on v ref+ supply v ref+ = 3.3 v, no load, middle code (0x800) 130 220 a v ref+ = 3.3 v, no load, worst code (0x000) 220 350 i vdda current consumption on v dda supply v dda = 3.3 v, no load, middle code (0x800) 210 320 v dda = 3.3 v, no load, worst code (0x000) 320 520 t a temperature range -40 125 c r l (1) (2) resistive load dacout buffer on 5 k r o output impedance dacout buffer off 8 10 k c l (3) capacitive load 50 pf dac_out (4) dac_out voltage dacout buffer on 0.2 v dda - 0.2 v dacout buffer off 0 v ref+ -1 lsb v t settling settling time (full scale: for a 12- bit input code transition between the lowest and the highest input codes when dac_out reaches the final value 1lsb ) r l 5 k , c l 50 pf 712s update rate max frequency for a correct dac_out (@95%) change when small variation of the input code (from code i to i+1lsb). r l 5k , c l 50 pf 1 msps t wakeup wakeup time from off state. input code between lowest and highest possible codes. r l 5k , c l 50 pf 915s psrr+ power supply rejection ratio (to v dda ) (static dc measurement ) r l 5k , c l 50 pf -60 -35 db 1. resistive load between dacout and gnda 2. output on pf0 or pf1 3. capacitive load at dacout pin 4. it gives the output excursion of the dac stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 111/129 in the following table, data based on characterization results, not tested in production. in the following table, data are guaranteed by design, not tested in production. table 51. dac accuracy symbol parameter conditions typ. max. unit dnl differential non linearity (1) r l 5k , c l 50 pf dacout buffer on (2) 1.5 3 12-bit lsb no load dacout buffer off 1.5 3 inl integral non linearity (3) r l 5k , c l 50 pf dacout buffer on (2) 24 no load dacout buffer off 24 offset offset error (4) r l 5k , c l 50 pf dacout buffer on (2) 10 25 no load dacout buffer off 5 8 offset1 offset error at code 1 (5) dacout buffer off 1.5 5 gain error gain error (6) r l 5k , c l 50 pf dacout buffer on (2) +0.1/-0.2 +0.2/-0.5 % no load dacout buffer off +0/-0.2 +0/-0.4 tue total unadjusted error r l 5k , c l 50 pf dacout buffer on (2) 12 30 12-bit lsb no load -dacout buffer off 8 12 1. difference between two consecutive codes - 1 lsb. 2. in 48-pin package devices the dac2 output buffer must be kept off and no load must be applied on the dac_out2 output. 3. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023. 4. difference between the value measured at code (0x800) and the ideal value = v ref+ /2. 5. difference between the value measured at code (0x001) and the ideal value. 6. difference between the ideal slope of the transfer functi on and the measured slope computed from code 0x000 and 0xfff when buffer is on, and from code giving 0.2 v and (v dda -0.2) v when buffer is off. table 52. dac output on pb4-pb5-pb6 (1) 1. 32 or 28-pin packages only. the da c channel can be routed either on pb4 , pb5 or pb6 using the routing interface i/o switch registers. symbol parameter conditions max unit r int internal resistance between dac output and pb4-pb5-pb6 output 2.7 v < v dd < 3.6 v 1.4 k 2.4 v < v dd < 3.6 v 1.6 2.0 v < v dd < 3.6 v 3.2 1.8 v < v dd < 3.6 v 8.2 electrical parameters stm8l15xx8, stm8l15xr6 112/129 doc id 17943 rev 5 9.3.14 12-bit adc1 characteristics in the following table, data are guaranteed by design, not tested in production. table 53. adc1 characteristics symbol parameter conditions min. typ. max. unit v dda analog supply voltage 1.8 3.6 v v ref+ reference supply voltage 2.4 v v dda 3.6 v 2.4 v dda v 1.8 v v dda 2.4 v v dda v v ref- lower reference voltage v ssa v i vdda current on the v dda input pin 1000 1450 a i vref+ current on the v ref+ input pin 400 700 (peak) (1) a 450 (average) (1) a v ain conversion voltage range 0 (2) v ref+ t a temperature range -40 125 c r ain external resistance on v ain on pf0/1/2/3 fast channels 50 (3) k on all other channels c adc internal sample and hold capacitor on pf0/1/2/3 fast channels 16 pf on all other channels f adc adc sampling clock frequency 2.4 v v dda 3.6 v without zooming 0.320 16 mhz 1.8 v v dda 2.4 v with zooming 0.320 8 mhz f conv 12-bit conversion rate v ain on pf0/1/2/3 fast channels 1 (3)(4) mhz v ain on all other channels 760 (3)(4) khz f trig external trigger frequency t conv 1/f adc t lat external trigger latency 3.5 1/f sysclk stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 113/129 t s sampling time v ain pf0/1/2/3 fast channels v dda < 2.4 v 0.43 (3)(4) s v ain pf0/1/2/3 fast channels 2.4 v v dda 3.6 v 0.22 (3)(4) s v ain on slow channels v dda < 2.4 v 0.86 (3)(4) s v ain on slow channels 2.4 v v dda 3.6 v 0.41 (3)(4) s t conv 12-bit conversion time 12 + t s 1/f adc 16 mhz 1 (3) s t wkup wakeup time from off state 3s t idle (5) time before a new conversion s t vrefint internal reference voltage startup time refer to ta bl e 4 6 ms 1. the current consumption through v ref is composed of two parameters: - one constant (max 300 a) - one variable (max 400 a), only during sa mpling time + 2 first conversion pulses. so, peak consumption is 300+400 = 700 a and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 a at 1msps 2. v ref- must be tied to ground. 3. minimum sampling and conversion time is reached for maximum r ain = 0.5 k . . 4. value obtained for continuous conversion on fast channel. 5. the time between 2 conversions, or between adc on and the first conversion must be lower than t idle. table 53. adc1 character istics (continued) symbol parameter conditions min. typ. max. unit electrical parameters stm8l15xx8, stm8l15xr6 114/129 doc id 17943 rev 5 in the following three tables, data are guaranteed by characterization result, not tested in production. table 54. adc1 accuracy with v dda = 3.3 v to 2.5 v symbol parameter conditions typ. max. unit dnl differential non linearity f adc = 16 mhz 1 1.6 lsb f adc = 8 mhz 1 1.6 f adc = 4 mhz 1 1.5 inl integral non linearity f adc = 16 mhz 1.2 2 f adc = 8 mhz 1.2 1.8 f adc = 4 mhz 1.2 1.7 tue total unadjusted error f adc = 16 mhz 2.2 3.0 f adc = 8 mhz 1.8 2.5 f adc = 4 mhz 1.8 2.3 offset offset error f adc = 16 mhz 1.5 2 lsb f adc = 8 mhz 1 1.5 f adc = 4 mhz 0.7 1.2 gain gain error f adc = 16 mhz 11.5 f adc = 8 mhz f adc = 4 mhz table 55. adc1 accuracy with v dda = 2.4 v to 3.6 v symbol parameter typ. max. unit dnl differential non linearity 1 2 lsb inl integral non linearity 1.7 3 lsb tue total unadjusted error 2 4 lsb offset offset error 1 2 lsb gain gain error 1.5 3 lsb table 56. adc1 accuracy with v dda = v ref + = 1.8 v to 2.4 v symbol parameter typ. max. unit dnl differential non linearity 1 2 lsb inl integral non linearity 2 3 lsb tue total unadjusted error 3 5 lsb offset offset error 2 3 lsb gain gain error 2 3 lsb stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 115/129 figure 42. adc1 accuracy characteristics figure 43. typical connection diagram using the adc 1. refer to ta b l e 5 3 for the values of r ain and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = a i c 3 4 - , x x x 6 $ $ ! ) . x ) , ? n ! 6 6 4 2 ! ) . # p a r a s i t i c 6 ! ) . 6 6 4 2 ! $ # # ! $ # b i t c o n v e r t e r 3 a m p l e a n d h o l d ! $ # c o n v e r t e r electrical parameters stm8l15xx8, stm8l15xr6 116/129 doc id 17943 rev 5 figure 44. maximum dynamic current consumption on v ref+ supply pin during adc conversion general pcb design guidelines power supply decoupling should be performed as shown in figure 45 or figure 46 , depending on whether v ref+ is connected to v dda or not. good quality ceramic 10 nf capacitors should be used. they should be placed as close as possible to the chip. adc clock sampling (n cycles) conversion (12 cycles) i ref+ 300a 700a table 57. r ain max for f adc = 16 mhz (1) ts (cycles) ts (s) r ain max (kohm) slow channels fast channels 2.4 v < v dda < 3.6 v 1.8 v < v dda < 2.4 v 2.4 v < v dda < 3.3 v 1.8 v < v dda < 2.4 v 4 0.25 not allowed not allowed 0.7 not allowed 9 0.5625 0.8 not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. guaranteed by design, not tested in production. stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 117/129 figure 45. power supply and reference decoupling (v ref+ not connected to v dda ) figure 46. power supply and reference decoupling (v ref+ connected to v dda ) v ref+ stm8l v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 nf ai17031 v ref+ /v dda stm8l 1 f // 10 nf v ref? /v ssa ai17032 electrical parameters stm8l15xx8, stm8l15xr6 118/129 doc id 17943 rev 5 9.3.15 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electromagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm iec61967-2 which specifies the board and the loading of each pin. table 58. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 using hsi 4a using hse 2b stm8l15xx8, stm8l15xr6 electrical parameters doc id 17943 rev 5 119/129 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and charge device model. this test conforms to the jesd22-a114a/a115a standard. static latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 59. emi data (1) 1. not tested in production. symbol parameter conditions monitored frequency band max vs. unit 16 mhz s emi peak level v dd = 3.6 v, t a = +25 c, lqfp80 conforming to iec61967-2 0.1 mhz to 30 mhz 10 db v 30 mhz to 130 mhz 4 130 mhz to 1 ghz 1 sae emi level 1.5 - table 60. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) 750 table 61. electrical sensitivities symbol parameter class lu static latch-up class ii electrical parameters stm8l15xx8, stm8l15xr6 120/129 doc id 17943 rev 5 9.4 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 18: general operating conditions on page 68 . the maximum chip-junction temperature, t jmax , in degree celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: t amax is the maximum ambient temperature in c ja is the package junction-to-ambient thermal resistance in c/w p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 62. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 48- 7 x 7 mm 65 c/w ja thermal resistance junction-ambient ufqfpn 48- 7 x 7mm 32 c/w ja thermal resistance junction-ambient lqfp 64- 10 x 10 mm 48 c/w ja thermal resistance junction-ambient lqfp 80- 14 x 14 mm 38 c/w stm8l15xx8, stm8l15xr6 package characteristics doc id 17943 rev 5 121/129 10 package characteristics 10.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. package characteristics stm8l15xx8, stm8l15xr6 122/129 doc id 17943 rev 5 figure 47. 80-pin low profile quad flat package (14 x 14 mm) table 63. 80-pin low profile quad flat package mechanical data symbol mm inches (1) 1. values in inches are converted fr om mm and rounded to four decimal places. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.220 0.320 0.380 0.0087 0.0126 0.0150 c 0.090 - 0.200 0.0035 - 0.0079 d 15.800 16.000 16.200 0.6220 0.6299 0.6378 d1 13.800 14.000 14.200 0.5433 0.5512 0.5591 d3 - 12.350 - - 0.4862 - e 15.800 16.000 16.200 0.6220 0.6299 0.6378 e1 13.800 14.000 14.200 0.5433 0.5512 0.5591 e3 - 12.350 - - 0.4862 - e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.100 - - 0.0039 4 , ! + , d " " c c c $ $ $ $ % % % b 0 i n i d e n t i f i c a t i o n - 3 6 stm8l15xx8, stm8l15xr6 package characteristics doc id 17943 rev 5 123/129 figure 48. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline (1) figure 49. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. , ! , d " " c c c $ $ $ % % % b 0 i n - 3 6 $ 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 64. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0. 0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 number of pins n64 1. values in inches are converted from mm and rounded to 4 decimal digits. package characteristics stm8l15xx8, stm8l15xr6 124/129 doc id 17943 rev 5 figure 50. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline (1) figure 51. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 table 65. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0. 0531 0.0551 0.0571 b 0.170 0.220 0.270 0. 0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0. 3465 0.3543 0.3622 d1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0. 3465 0.3543 0.3622 e1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0. 0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. stm8l15xx8, stm8l15xr6 package characteristics doc id 17943 rev 5 125/129 figure 52. ufqfpn48 7 x 7 mm, 0.5 mm pitch, package outline (1)(2)(3) figure 53. recommended footprint (dimensions in mm) (1) 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pcb to improve the lead/pad solder joint life. 3. there is an exposed die pad on the underside of the ufqfpn package. it is recommended to connect and solder this back-side pad to pcb ground. 3 e a t i n g p l a n e ! ! ! ! $ e e % b % , , $ b ! " ? - % # 7.30 7.30 0.20 0.30 0.55 0.50 5.80 6.20 6.20 5.60 5.60 5.80 0.75 ai15697 48 1 12 13 24 25 36 37 table 66. ufqfpn48 ? ultra thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm pitch package mechanical data symbol millimeters inches (1) typ min max typ min max a 0.550 0.500 0.600 0.02170 0.01970 0.0236 a1 0.020 0 0.050 0.0008 0 0.0020 a2 0.530 0.500 0.550 0.0209 0.0197 0.0217 a3 0.150 0.140 0.160 0.0059 0.0055 0.0063 b 0.230 0.180 0.300 0.0091 0.0071 0.0118 d 7.000 6.850 7.150 0.2756 0.2697 0.2815 d2 4.700 2.250 5.250 0.1850 0.0886 0.2067 e 7.000 6.850 7.150 0.2756 0.2697 0.2815 e2 4.700 2.250 5.250 0.1850 0.0886 0.2067 e 0.500 0.450 0.550 0.0197 0.0177 0.0217 l 0.400 0.300 0.500 0.0157 0.0118 0.0197 ddd 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. ordering information scheme stm8l15xx8, stm8l15xr6 126/129 doc id 17943 rev 5 11 ordering information scheme for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the st sales office nearest to you . table 67. ordering information scheme example: stm8 l 152 c 8 t 6 d device family stm8 microcontroller product type l = low power device subfamily 151: devices without lcd 152: devices with lcd pin count c = 48 pins r = 64 pins m = 80 pins program memory size 8 = 64 kbytes of flash memory 6 = 32 kbytes package t = lqfp u= ufqfpn temperature range 3 = industrial temperature range, ? 40 to 125 c 7 = industrial temperature range, ? 40 to 105 c 6 = industrial temperature range, ? 40 to 85 c option blank = v dd range from 1.8 to 3.6 v and bor enabled d = v dd range from 1.65 to 3.6 v and bor disabled stm8l15xx8, stm8l15xr6 revision history doc id 17943 rev 5 127/129 12 revision history table 68. document revision history date revision changes 13-sep-2010 1 initial release. 20-dec-2010 2 updated section 9.3.3: supply cu rrent characteristics updated section 9.3.2: embedded reset and power control block characteristics . updated section 9.3.3: supply cu rrent characteristics updated section 9.3.13: 12-bit dac characteristics updated section 9.3.14: 12-bit adc1 characteristics updated section 9.3.15: em c characteristics 17-jan-2011 3 removed references to stm8l150m8 devices. 11-mar-2011 4 updated table 1: device summary . table 5: high density and medium+ d ensity stm8l15x pin description : updated pb4/43&35, pb4/28, pc1, pi 3, and pins 33 to 36 of lqfp80; updated footnotes. timx_trig changed to timx_etr and ?standard port? changed to ?high sink port?. table 15: voltage characteristics : updated table 16: current characteristics : updated table 35: ram and hardware registers : updated vrm data min. retention. added table 9.3.6: i/o current injection characteristics . table 38: i/o static characteristics : updated table 45: lcd characteristics : updated revision history stm8l15xx8, stm8l15xr6 128/129 doc id 17943 rev 5 03-apr-2013 5 updated capacitive sensing channel s and ?dynamic c onsumption? in features updated lcd feature in table 2: high density and medium+ density stm8l15xx low power device features and peripheral counts updated halt mode definition in section 3.1: low power modes added bootloader updated section 3.12: system configur ation controller and routing interface added section 3.13: touch sensing table 5: high density and medium+ d ensity stm8l15x pin description : updated nrst/pa1, pi0, pi1, pi2, pe0, pe1, pe2, pf4, pf5, pf6, pf7, footnote 1. and added note: updated ?0x00 502e to 0x00 5049? reserved area in table 9: general hardware register map updated reference to swim/debug manual in section 7: option bytes updated bor factory default settings to 0x00 in table 12: option byte addresses corrected rop option byte value in table 12: option byte addresses added figure 44: maximum dynamic current consumption on v ref+ supply pin during adc conversion updated stabvrefint max value in table 46: reference voltage characteristics updated figure 40: spi1 timing diagram - master mode added ta bl e 5 7 : r ain max for f adc = 16 mhz updated max dac_out in table 50: dac characteristics updated section 9.3.12: compar ator characteristics table 68. document revision history (continued) date revision changes stm8l15xx8, stm8l15xr6 doc id 17943 rev 5 129/129 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not authorized for use in weapons. nor are st products designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? 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